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公开(公告)号：US11139843B1
公开(公告)日：2021-10-05
申请号：US16927537
申请日：2020-07-13
Applicant: QUALCOMM Incorporated
IPC: H04L27/00 , H04B1/04 , H03K19/0185
Abstract: Certain aspects of the present disclosure generally relate to a driver circuit for a serializer/deserializer (SerDes) transmitter and techniques for operating such a driver circuit. One example driver circuit generally includes a pre-driver circuit, an output stage circuit, and a common-gate buffer circuit coupled between an output of the pre-driver circuit and a first input of the output stage circuit.
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公开(公告)号：US10084621B2
公开(公告)日：2018-09-25
申请号：US15422050
申请日：2017-02-01
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Zhi Zhu , Miao Li , Li Sun , Deqiang Song , Chia Heng Chang
Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
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公开(公告)号：US20160246317A1
公开(公告)日：2016-08-25
申请号：US14630481
申请日：2015-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Dinesh Jagannath Alladi , Dan Yuan
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: In one embodiment, a method for generating a reference comprises generating a current that is approximately temperature independent over a temperature range based on an emitter-base voltage of a first bipolar junction transistor (BJT), and generating a first proportional to absolute temperature (PTAT) current based on the emitter-base voltage of the first BJT.
Abstract translation: 在一个实施例中，用于产生参考的方法包括基于第一双极结型晶体管（BJT）的发射极 - 基极电压产生在温度范围上近似温度独立的电流，并产生与绝对温度成比例的第一（PTAT ）电流基于第一BJT的发射极 - 基极电压。
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公开(公告)号：US09024684B2
公开(公告)日：2015-05-05
申请号：US13831639
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/0802 , H03L7/087 , H03L7/0891 , H03L7/0893 , H03L7/093
Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
Abstract translation: 本文描述了用于降低锁相环（PLL）的环路滤波器中的噪声和功耗的技术。 在一个实施例中，用于PLL的环路滤波器包括第一比例电容器，第二比例电容器，有源器件和多个开关。 多个开关被配置为将第一比例电容器和第二比例电容器交替地耦合到第一电荷泵，以将来自有源器件的噪声交替耦合到第一比例电容器和第二比例电容器，并且交替地耦合第一比例电容器 电容器和第二比例电容器组成反馈电路，其中反馈电路产生环路滤波器的输出电压。
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公开(公告)号：US11923861B1
公开(公告)日：2024-03-05
申请号：US18164211
申请日：2023-02-03
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/0995 , H03L7/0891 , H03L7/091
Abstract: A voltage controlled oscillator (VCO), including: at least one second upper voltage rail; at least one second lower voltage rail; a ring of N cascaded inverters, wherein the set of N cascaded inverters are coupled between the at least one second upper voltage rail and the at least one second lower voltage rail; at least one first frequency band select circuit coupled between first upper voltage rail and the at least one second upper voltage rail; at least one second frequency band select circuit coupled between the at least one second lower voltage rail and first lower voltage rail; at least one first VCO frequency control circuit coupled between the first upper voltage rail and the at least one second upper voltage rail; and at least one second VCO frequency control circuit coupled between the at least one second lower voltage rail and the first lower voltage rail.
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Patent Agency Ranking
公开(公告)号：US09401707B1
公开(公告)日：2016-07-26
申请号：US14675936
申请日：2015-04-01
Applicant: QUALCOMM Incorporated
IPC: H03K17/16
CPC classification number: H03K17/165 , H03F1/0233 , H03F1/307 , H03F1/3217 , H03F3/26
Abstract: A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.
Abstract translation: 推挽驱动器设置有差分放大器，其放大输入电压和输出电压之间的差以驱动耦合到二极管连接的偏置晶体管的偏置节点。 推挽驱动器被配置为控制源极跟随器输出晶体管的漏极 - 源极电压，其栅极连接到二极管连接的偏置晶体管的栅极与源极 - 源极电压成比例 二极管连接的偏置晶体管。 这种比例性可以防止在源极跟随器输出晶体管中存在的过大的静态电流变化。
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公开(公告)号：US09086711B2
公开(公告)日：2015-07-21
申请号：US13740539
申请日：2013-01-14
Applicant: QUALCOMM Incorporated
Inventor： Jan Diffenderfer , Yu Song
IPC: H04B1/28 , G05F1/46 , H03K3/3565 , H03K19/0185
CPC classification number: G05F1/46 , H03K3/3565 , H03K19/018521
Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.
Abstract translation: 本文公开了单端比较器。 比较器可以利用能够在输入处与高电压信号一起工作的低压半导体器件来实现。 单端比较器可以集成在更大的电路中，以接收和检测在电路电平上提供的信号，该电平高于由电路其余部分支持的电平，并传送接收信号中的信息供其余部分使用 电路。
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公开(公告)号：US20140266343A1
公开(公告)日：2014-09-18
申请号：US13831639
申请日：2013-03-15
Applicant: Qualcomm Incorporated
IPC: H03L7/08
CPC classification number: H03L7/0802 , H03L7/087 , H03L7/0891 , H03L7/0893 , H03L7/093
Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
Abstract translation: 本文描述了用于降低锁相环（PLL）的环路滤波器中的噪声和功耗的技术。 在一个实施例中，用于PLL的环路滤波器包括第一比例电容器，第二比例电容器，有源器件和多个开关。 多个开关被配置为将第一比例电容器和第二比例电容器交替地耦合到第一电荷泵，以将来自有源器件的噪声交替耦合到第一比例电容器和第二比例电容器，并且交替地耦合第一比例电容器 电容器和第二比例电容器组成反馈电路，其中反馈电路产生环路滤波器的输出电压。
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9.发明授权公开(公告)号：US11646917B1
公开(公告)日：2023-05-09
申请号：US17563989
申请日：2021-12-28
Applicant: QUALCOMM Incorporated
Inventor： Younwoong Chung , Yu Song , Minghsien Tsai , Zhi Zhu
CPC classification number: H04L25/03057 , H04L7/0079 , H04L7/04
Abstract: An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.
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公开(公告)号：US11206012B2
公开(公告)日：2021-12-21
申请号：US17101685
申请日：2020-11-23
Applicant: QUALCOMM Incorporated
IPC: H03K3/012 , G11C11/4093 , H03K17/687 , H03F3/45
Abstract: A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.
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