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    Bias Circuit for Comparators
    2.
    发明申请
    Bias Circuit for Comparators 审中-公开
    比较器偏置电路

    公开(公告)号：US20160087607A1

    公开(公告)日：2016-03-24

    申请号：US14495744

    申请日：2014-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Wei Huang ,  Yuhua Guo

    IPC: H03K3/011 ,  H03K5/24

    CPC classification number: H03K5/2481 ,  H03K3/023

    Abstract: Pumping current into a regeneration latch of a comparator, including: a first transistor configured to receive a first constant current from a first constant current source; a first current mirror coupled to the first transistor and configured to provide a first bias current, wherein the first transistor substantially mirrors the first constant current into the first bias current in the first current mirror; a second transistor configured to receive a second constant current from a second constant current source; a second current mirror coupled to the second transistor and configured to provide a second bias current, wherein the second transistor substantially mirrors the second constant current into the second bias current in the second current mirror; and a third transistor configured to combine the first bias current and the second bias current, wherein the third transistor pumps the combined bias current into the regeneration latch.

    Abstract translation: 将电流泵送到比较器的再生锁存器中，包括：第一晶体管，被配置为从第一恒定电流源接收第一恒定电流; 耦合到所述第一晶体管并被配置为提供第一偏置电流的第一电流镜，其中所述第一晶体管基本上将所述第一恒定电流反射到所述第一电流镜中的所述第一偏置电流; 第二晶体管，被配置为从第二恒定电流源接收第二恒定电流; 耦合到所述第二晶体管并被配置为提供第二偏置电流的第二电流镜，其中所述第二晶体管基本上将所述第二恒定电流反射到所述第二电流镜中的所述第二偏置电流; 以及第三晶体管，被配置为组合所述第一偏置电流和所述第二偏置电流，其中所述第三晶体管将所述组合的偏置电流泵送到所述再生锁存器中。

    VOLTAGE LEVEL SHIFTER WITH A LOW-LATENCY VOLTAGE BOOST CIRCUIT
    3.
    发明申请
    VOLTAGE LEVEL SHIFTER WITH A LOW-LATENCY VOLTAGE BOOST CIRCUIT 有权
    具有低电压电压升压电路的电压等级变换器

    公开(公告)号：US20140253210A1

    公开(公告)日：2014-09-11

    申请号：US13787590

    申请日：2013-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh J. Alladi ,  Yuhua Guo

    IPC: H03K5/156 ,  H03K3/012 ,  H03L5/00

    CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

    Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

    Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

    Low noise and low power passive sampling network for a switched-capacitor ADC with a slow reference generator
    5.
    发明授权
    Low noise and low power passive sampling network for a switched-capacitor ADC with a slow reference generator 有权
    低噪声和低功耗的无源采样网络，用于带缓慢参考发生器的开关电容ADC

    公开(公告)号：US09411987B2

    公开(公告)日：2016-08-09

    申请号：US14826928

    申请日：2015-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Dinesh Jagannath Alladi ,  Yuhua Guo

    IPC: H03M3/00 ,  G06G7/186

    CPC classification number: G06G7/186 ,  G06G7/1865 ,  H03M3/32 ,  H03M3/342 ,  H03M3/344 ,  H03M3/496 ,  H03M3/50

    Abstract: Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

    Abstract translation: 本公开的某些方面提供用于开关电容器积分器的各种采样网络，其可用于开关电容器模数转换器（ADC）。 不同于输入采样电容器和参考采样电容器两者，本公开的某些方面使用共享采样电容器作为参考电压和输入电压，从而减少ADC输入参考噪声，降低运算放大器面积和功率，以及 避免抗混叠滤波器插入损耗。 此外，通过在采样阶段对参考电压进行采样并使用共享采样电容在积分阶段对输入电压进行采样，高参考电压不需要用于参考电压。

    Voltage level shifter with a low-latency voltage boost circuit
    7.
    发明授权
    Voltage level shifter with a low-latency voltage boost circuit 有权
    具有低延时升压电路的电压电平转换器

    公开(公告)号：US09306553B2

    公开(公告)日：2016-04-05

    申请号：US13787590

    申请日：2013-03-06

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh Jagannath Alladi ,  Yuhua Guo

    IPC: H03L5/00 ,  H03K5/156 ,  H03K3/012 ,  H03K3/356 ,  H03K19/017 ,  H03K19/0185

    CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

    Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

    Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

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