公开(公告)号：US07655555B2

公开(公告)日：2010-02-02

申请号：US09895520

申请日：2001-06-28

Applicant: Richard A. Faust ,  Qing-Tang Jiang ,  Jiong-Ping Lu

Inventor： Richard A. Faust ,  Qing-Tang Jiang ,  Jiong-Ping Lu

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/28

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/76807 ,  H01L21/76843

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.

Abstract translation: 具有过渡金属 - 氮化硅屏障（106）的铜互连。 过渡金属氮化物通过在含Si环境中的反应性溅射与Si共沉积以形成势垒（106）。 然后，铜（110）以良好的粘附性沉积在过渡金属 - 氮化硅屏障（108）上。

公开(公告)号：US06784104B2

公开(公告)日：2004-08-31

申请号：US10194592

申请日：2002-07-12

Applicant: Qing-Tang Jiang ,  Jiong-Ping Lu

Inventor： Qing-Tang Jiang ,  Jiong-Ping Lu

IPC: H10L214763

CPC classification number: H01L21/76888 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76886

Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.

Abstract translation: 铜的电镀是在集成电路上形成铜线的领先技术。 在铜电镀工艺中，半导体晶片的表面作为阴极施加负电位至半导体晶片。 阳极将部分或全部由铜形成。 阳极和半导体都将暴露于包含铜电解质的溶液中。 通过将铜电解质溶液的温度降低到25℃以下，自退火晶粒生长速率将会降低铜线的最终电阻。

公开(公告)号：US06958290B2

公开(公告)日：2005-10-25

申请号：US10138393

申请日：2002-05-03

Applicant: Richard A. Faust, Jr. ,  Qing-Tang Jiang ,  Jiong-Ping Lu

Inventor： Richard A. Faust, Jr. ,  Qing-Tang Jiang ,  Jiong-Ping Lu

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract translation: 在集成器件中，在衬底层中形成通孔，并且在通孔中的衬底层上形成阻挡层。 在通孔的阻挡层上形成种子层。 种子层包括第一材料和第二材料。 第一种材料提供了使第二种材料保持与阻挡层粘合的能力。

公开(公告)号：US06586334B2

公开(公告)日：2003-07-01

申请号：US09975571

申请日：2001-10-11

Applicant: Qing-Tang Jiang

Inventor： Qing-Tang Jiang

IPC: H01L2144

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76844

Abstract: A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106). The thin liner (110, 210, 310) smoothes the sidewalls of the trench (108) and/or via (106) and reduces resistivity. The thin liner may comprise an organic or inorganic dielectric (110) or metal (210,310). A copper interconnect structure (116, 216, 316) is then formed over the thin liner (110, 210, 310).

公开(公告)号：US06951812B2

公开(公告)日：2005-10-04

申请号：US10739980

申请日：2003-12-17

Applicant: Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

Inventor： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Abstract translation: 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06911394B2

公开(公告)日：2005-06-28

申请号：US10340932

申请日：2003-01-13

Applicant: Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

Inventor： Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供半导体衬底（202），在半导体衬底（202）上形成电介质层（204），以及蚀刻电介质层（204）中的沟槽或通孔（206） ）以暴露半导体衬底（202）的表面的一部分。 该方法还包括在沟槽或通孔（206）内形成导电层（212,220）的步骤。 该方法还包括以下步骤：抛光导电层（220）的一部分并在预定温度下退火导电层（212,220）。 此外，导电层（212,220）还包括掺杂剂，并且掺杂剂基本上扩散到导电层（212,220）的顶侧的表面，以形成掺杂剂氧化物层（212a，220a），当 导电层（212,220）在预定温度下退火，掺杂剂暴露于氧气。

公开(公告)号：US07187080B2

公开(公告)日：2007-03-06

申请号：US10964963

申请日：2004-10-14

Applicant: Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

Inventor： Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

IPC: H01L23/48

CPC classification number: H01L21/76844 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供半导体衬底（202），在半导体衬底（202）上形成电介质层（204），并蚀刻电介质层（204）中的沟槽或通孔（206） ）以暴露半导体衬底（202）的表面的一部分。 该方法还包括在沟槽或通孔（206）内形成导电层（212,220）的步骤。 该方法还包括以下步骤：抛光导电层（220）的一部分并在预定温度下退火导电层（212,220）。 此外，导电层（212,220）还包括掺杂剂，并且掺杂剂基本上扩散到导电层（212,220）的顶侧的表面，以形成掺杂剂氧化物层（212a，220a），当 导电层（212,220）在预定温度下退火，掺杂剂暴露于氧气。

公开(公告)号：US06693356B2

公开(公告)日：2004-02-17

申请号：US10107630

申请日：2002-03-27

Applicant: Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

Inventor： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC: H01L2352

CPC classification number: H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Abstract translation: 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06548400B2

公开(公告)日：2003-04-15

申请号：US09917364

申请日：2001-07-27

Applicant: Kenneth D. Brennan ,  Qing-Tang Jiang

Inventor： Kenneth D. Brennan ,  Qing-Tang Jiang

IPC: H01L214763

CPC classification number: H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted. As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.

Abstract translation: 一种用于在集成电路中制造电路互连的方法，其包括金属线之间的垂直通孔和水平沟槽，其中仅需要一个用于产生通路和沟槽的光掩模，而不是传统的两个掩模。 第二掩模的功能被一系列等离子体蚀刻步骤代替，这些步骤利用相对于狭窄和收缩的区域开放的区域的差别蚀刻速率。作为本发明的技术优点，每个互连通过 本发明是更宽的沟槽和较窄通孔的结构，其中通孔的直径与反向沟槽图案的最窄宽度大致相同，并且每个通孔在沟槽内居中。 围绕通孔的反向沟槽图案大约是通孔直径宽度的两倍。

公开(公告)号：US20050048784A1

公开(公告)日：2005-03-03

申请号：US10964963

申请日：2004-10-14

Applicant: Qing-Tang Jiang ,  Changming Jin ,  J. Luttmer

Inventor： Qing-Tang Jiang ,  Changming Jin ,  J. Luttmer

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8238

CPC classification number: H01L21/76844 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供半导体衬底（202），在半导体衬底（202）上形成电介质层（204），并蚀刻电介质层（204）中的沟槽或通孔（206） ）以暴露半导体衬底（202）的表面的一部分。 该方法还包括在沟槽或通孔（206）内形成导电层（212,220）的步骤。 该方法还包括以下步骤：抛光导电层（220）的一部分并在预定温度下退火导电层（212,220）。 此外，导电层（212,220）还包括掺杂剂，并且掺杂剂基本上扩散到导电层（212,220）的顶侧的表面以形成掺杂剂氧化物层（212a，220a），当导电 层（212,220）在预定温度下退火，掺杂剂暴露于氧气。