公开(公告)号：US11830944B2

公开(公告)日：2023-11-28

申请号：US17380682

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/045 ,  H01L29/66681

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US12266727B2

公开(公告)日：2025-04-01

申请号：US18490473

申请日：2023-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US11114527B2

公开(公告)日：2021-09-07

申请号：US16815636

申请日：2020-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Hideki Niwayama ,  Kazuyuki Umezu ,  Hiroki Soeda ,  Atsushi Tachigami ,  Takeshi Iijima

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

公开(公告)号：US10790388B2

公开(公告)日：2020-09-29

申请号：US16036434

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Makoto Koshimizu ,  Komaki Inoue ,  Hideki Niwayama

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/324 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285

Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.

公开(公告)号：US12293925B2

公开(公告)日：2025-05-06

申请号：US17894579

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki Murayama ,  Makoto Koshimizu ,  Takahiro Mori ,  Junjiro Sakai ,  Satoshi Iida

IPC: H01L21/4757 ,  H01L21/311 ,  H01L21/475 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

公开(公告)号：US11594489B2

公开(公告)日：2023-02-28

申请号：US16668802

申请日：2019-10-30

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu Hanawa ,  Kazuhide Fukaya ,  Makoto Koshimizu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.

公开(公告)号：US09349827B2

公开(公告)日：2016-05-24

申请号：US14718695

申请日：2015-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi Matsuura ,  Makoto Koshimizu ,  Yoshito Nakazawa

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/36 ,  H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L29/16

CPC classification number: H01L29/66348 ,  H01L21/265 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7397 ,  H01L29/8611

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N−-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N−-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N−-type drift region. The N−-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N−-type drift region.

公开(公告)号：US12142679B2

公开(公告)日：2024-11-12

申请号：US17722778

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

公开(公告)号：US12015053B2

公开(公告)日：2024-06-18

申请号：US17717724

申请日：2022-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L29/7823 ,  H01L29/66681

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.