公开(公告)号：US20130292815A1

公开(公告)日：2013-11-07

申请号：US13939766

申请日：2013-07-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukinori TASHIRO ,  Yoshinori MIYAKI

IPC: H01L23/495

CPC classification number: H01L21/561 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/14836 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06143 ,  H01L2224/06145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2224/85 ,  H01L2224/48471 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/20752 ,  H01L2224/4554

Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire.In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.

Abstract translation: 为了抑制在将线路板和安装在其主表面上的一个半导体芯片与导线电耦合的半导体器件中的线形成多级时引起的相邻导线之间的短路。 在其中芯片安装在布线板的上表面上的布线板的接合引线和芯片的焊盘与电线电耦合的半导体器件中，通过制造相邻布线之间的短路来抑制 放置在最靠近芯片角部的位置的最长的线的直径大于其它线的直径。

公开(公告)号：US20180323168A1

公开(公告)日：2018-11-08

申请号：US16032825

申请日：2018-07-11

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori MIYAKI ,  Masaru YAMADA

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/97 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.

公开(公告)号：US20200098679A1

公开(公告)日：2020-03-26

申请号：US16547294

申请日：2019-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki SATO ,  Yoshinori MIYAKI ,  Junichi ARITA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.