公开(公告)号：US20130292815A1

公开(公告)日：2013-11-07

申请号：US13939766

申请日：2013-07-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukinori TASHIRO ,  Yoshinori MIYAKI

IPC: H01L23/495

CPC classification number: H01L21/561 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/14836 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06143 ,  H01L2224/06145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2224/85 ,  H01L2224/48471 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/20752 ,  H01L2224/4554

Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire.In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.

Abstract translation: 为了抑制在将线路板和安装在其主表面上的一个半导体芯片与导线电耦合的半导体器件中的线形成多级时引起的相邻导线之间的短路。 在其中芯片安装在布线板的上表面上的布线板的接合引线和芯片的焊盘与电线电耦合的半导体器件中，通过制造相邻布线之间的短路来抑制 放置在最靠近芯片角部的位置的最长的线的直径大于其它线的直径。

公开(公告)号：US20170287737A1

公开(公告)日：2017-10-05

申请号：US15428176

申请日：2017-02-09

Applicant: Renesas Electronics Corporation

Inventor： Yukinori TASHIRO

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/544 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/565 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/2708 ,  H01L21/4853 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.

公开(公告)号：US20180226275A1

公开(公告)日：2018-08-09

申请号：US15948255

申请日：2018-04-09

Applicant: Renesas Electronics Corporation

Inventor： Yukinori TASHIRO

IPC: H01L21/56 ,  H01L23/00 ,  B29C45/14 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/544 ,  H01L23/498 ,  B29C45/00 ,  B29C45/27

CPC classification number: H01L21/565 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/2708 ,  H01L21/4853 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The reliability of a semiconductor device is improved.During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.