公开(公告)号：US12107138B2

公开(公告)日：2024-10-01

申请号：US18059603

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391

Abstract: To improve a reliability of a nonvolatile memory cell including a ferroelectric film. The nonvolatile memory cell MC includes a paraelectric film IL formed on a semiconductor substrate SUB, the ferroelectric film FE formed on the paraelectric film IL, a gate electrode GE formed on the ferroelectric film FE, a high dielectric constant film HK formed on the ferroelectric film FE such that the high dielectric constant film HK cover side surfaces of the gate electrode GE, and a source region SR and a drain region DR formed in an upper surface of the semiconductor substrate SUB such that the ferroelectric film FE is sandwiched between the source region SR and the drain region DR. A relative dielectric constant of the high dielectric constant film HK is higher than a relative dielectric constant of the ferroelectric film FE.

公开(公告)号：US11302828B2

公开(公告)日：2022-04-12

申请号：US17084163

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

公开(公告)号：US10483276B2

公开(公告)日：2019-11-19

申请号：US16020094

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima ,  Atsushi Yoshitomi

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/423

Abstract: To provide a semiconductor device capable of having an ONO-film-configuring second oxide film with an optimized thickness. The semiconductor device has a semiconductor substrate having a first surface, a first gate insulating film placed on the first surface located in a first transistor formation region, and a second gate insulating film placed on the first surface located in a second transistor formation region. The first gate insulating film has a first oxide film, a first nitride film placed thereon, and a second oxide film placed thereon. The second oxide film includes a first layer and a second layer placed thereon. The height of the first surface in a region where the second insulating film is placed is lower than that in a region where the first gate insulating film is placed. The nitrogen concentration in the first layer is higher than that in the second layer.

公开(公告)号：US09520504B2

公开(公告)日：2016-12-13

申请号：US14190183

申请日：2014-02-26

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L29/792 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.

Abstract translation: 在具有分离栅极结构的MONOS型存储单元中，防止了选择栅电极和存储栅电极之间的短路，提高了半导体器件的可靠性。 在具有彼此相邻并且沿第一方向延伸的选择栅电极和存储栅电极的MONOS存储器中，在除了在第一方向的端部处的分流部分之外的区域中的选择栅电极的上表面 第一方向的选择栅极电极被帽绝缘膜覆盖。 存储栅电极相对于帽绝缘膜与从帽绝缘膜露出的分流部的上表面之间的边界在帽绝缘膜侧终止。

公开(公告)号：US09412748B2

公开(公告)日：2016-08-09

申请号：US14829605

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Hayashi ,  Yoshiyuki Kawashima

IPC: H01L21/8238 ,  H01L27/115 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/3247 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/6656

Abstract: An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode and a memory gate electrode which are formed over a semiconductor substrate as a mask, n-type impurity ions are implanted from a direction perpendicular to a main surface of the semiconductor substrate. Then, using the control gate electrode, the memory gate electrode, and first and second sidewall spacers as a mask, other n-type impurity ions are implanted from a direction inclined relative to the direction perpendicular to the main surface of the semiconductor substrate.

Abstract translation: 在半导体器件的性能方面实现了改进。 在制造半导体器件的方法中，使用形成在半导体衬底上的控制栅电极和存储栅电极作为掩模，从垂直于半导体衬底的主表面的方向注入n型杂质离子。 然后，使用控制栅电极，存储栅电极以及第一和第二侧壁间隔件作为掩模，从相对于与半导体衬底的主表面垂直的方向倾斜的方向注入其它n型杂质离子。

公开(公告)号：US20160204116A1

公开(公告)日：2016-07-14

申请号：US15073524

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

公开(公告)号：US20160043098A1

公开(公告)日：2016-02-11

申请号：US14804305

申请日：2015-07-20

Applicant: Renesas Electronics Corporation

Inventor： Nobuto Nakanishi ,  Yoshiyuki Kawashima ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/45 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31053 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n− type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming n+ type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the n+ type semiconductor regions.

Abstract translation: 提供具有提高的可靠性的半导体器件。 提供一种通过第一绝缘膜在半导体衬底上形成用于存储单元的控制栅电极的半导体器件; 通过具有电荷存储部分的第二绝缘膜，在半导体衬底上形成与控制栅电极相邻的用于存储单元的存储栅电极; 通过离子注入在半导体衬底中形成用于源极或漏极的n-型半导体区域; 在控制栅电极和存储栅电极的侧壁上形成侧壁间隔物; 通过离子注入在半导体衬底中形成用于源极或漏极的n +型半导体区域; 以及去除存在于控制栅电极和存储栅电极之间的第二绝缘膜的上部。 第二绝缘膜的去除长度大于n +型半导体区域的深度。

公开(公告)号：US20160035734A1

公开(公告)日：2016-02-04

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。

公开(公告)号：US20150287736A1

公开(公告)日：2015-10-08

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜形成。 以及位于第一硅区上方的第二硅区。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US20140239378A1

公开(公告)日：2014-08-28

申请号：US14190183

申请日：2014-02-26

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.

Abstract translation: 在具有分离栅极结构的MONOS型存储单元中，防止了选择栅电极和存储栅电极之间的短路，提高了半导体器件的可靠性。 在具有彼此相邻并且沿第一方向延伸的选择栅电极和存储栅电极的MONOS存储器中，在除了在第一方向的端部处的分流部分之外的区域中的选择栅电极的上表面 第一方向的选择栅极电极被帽绝缘膜覆盖。 存储栅电极相对于帽绝缘膜与从帽绝缘膜露出的分流部的上表面之间的边界在帽绝缘膜侧终止。