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公开(公告)号：US20190244763A1
公开(公告)日：2019-08-08
申请号：US16385876
申请日：2019-04-16
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki OKADA , Yasuhiro FUWA
Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.
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2.发明申请公开(公告)号：US20160087027A1
公开(公告)日：2016-03-24
申请号：US14956939
申请日：2015-12-02
Applicant: ROHM CO., LTD.
Inventor： Hiroshi TAMAGAWA , Yasuhiro KONDO , Yasuhiro FUWA , Hiroyuki OKADA , Eiji NUKAGA , Katsuya MATSUURA
IPC: H01L49/02 , H01L21/3065
CPC classification number: H01L28/20 , H01C1/14 , H01C13/02 , H01C17/006 , H01C17/242 , H01L21/3065 , H01L21/3083 , H01L27/0676 , H01L27/0802 , H05K3/3431 , H05K2201/10674
Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
Abstract translation: 希望能够以相同的设计结构容易地容纳多种类型的所需电阻值的紧凑且精细的芯片电阻器。 芯片电阻被布置成在基板上具有电阻网络。 电阻网络包括排列成矩阵并具有相等电阻值的多个电阻体。 多个电阻单元分别由电气连接的一个或多个电阻体排列。 多种类型的电阻单元使用连接导体膜和熔丝膜以预定模式连接。 通过选择性地熔断保险膜，可以将电阻单元电连接到电阻网络中或与电阻网络电隔离，使电阻网络的电阻值成为所需的电阻值。
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Patent Agency Ranking
公开(公告)号：US20190148480A1
公开(公告)日：2019-05-16
申请号：US16250453
申请日：2019-01-17
Applicant: ROHM CO., LTD.
Inventor： Hiroshi TAMAGAWA , Yasuhiro KONDO , Yasuhiro FUWA , Hiroyuki OKADA , Eiji NUKAGA , Katsuya MATSUURA
IPC: H01L49/02 , H01L21/3065 , H01L21/308 , H01C13/02 , H01C1/14 , H01L27/06 , H01L27/08
Abstract: [Theme] A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
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公开(公告)号：US20170365655A1
公开(公告)日：2017-12-21
申请号：US15647592
申请日：2017-07-12
Applicant: ROHM CO., LTD.
Inventor： Hiroshi TAMAGAWA , Yasuhiro KONDO , Yasuhiro FUWA , Hiroyuki OKADA , Eiji NUKAGA , Katsuya MATSUURA
IPC: H01L49/02 , H01C13/02 , H01L21/3065 , H01L27/08 , H01L27/06 , H01L21/308 , H01C1/14 , H05K3/34 , H01C17/00 , H01C17/242
CPC classification number: H01L28/20 , H01C1/14 , H01C13/02 , H01C17/006 , H01C17/242 , H01L21/3065 , H01L21/3083 , H01L27/0676 , H01L27/0802 , H05K3/3431 , H05K2201/10674
Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
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公开(公告)号：US20180174759A1
公开(公告)日：2018-06-21
申请号：US15836208
申请日：2017-12-08
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki OKADA , Yasuhiro FUWA
CPC classification number: H01G5/011 , H01G4/015 , H01G4/33 , H01G4/385 , H01G4/40 , H01G5/38 , H01L27/016 , H01L28/40
Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.
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公开(公告)号：US20170301436A1
公开(公告)日：2017-10-19
申请号：US15485640
申请日：2017-04-12
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki OKADA , Yasuhiro KONDO
Abstract: A chip resistor including, a substrate having a main surface, a first resistance circuit formed at the main surface of the substrate, a second resistance circuit formed at the main surface of the substrate apart from the first resistance circuit, a common internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit and the second resistance circuit, a first internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit, a second internal electrode formed at the main surface of the substrate and electrically connected to the second resistance circuit, and a dummy resistance circuit formed in a region between the first resistance circuit and the second resistance circuit at the main surface of the substrate so as to be in an electrically floating state.
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公开(公告)号：US20170019083A1
公开(公告)日：2017-01-19
申请号：US15212221
申请日：2016-07-16
Applicant: ROHM CO., LTD.
Inventor： Keisuke FUKAE , Yasuhiro KONDO , Katsuya MATSUURA , Hiroyuki OKADA , Junya YAMAGAMI
CPC classification number: H03H7/06 , H03H1/02 , H03H2001/0085
Abstract: A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.
Abstract translation: 滤波器芯片包括基板，形成在用于外部连接的基板上的多个外部端子，以及当沿着垂直于该表面的方向观察时设置在多个外部端子之间的区域中的多个无源元件形成区域 所述多个无源元件形成区域至少包括形成电阻器的电阻器形成区域。 电阻器形成区域包括形成在基板上的电阻导电膜，其一端并且另一端电连接到不同的外部端子，以及与电阻导电膜一体形成的熔丝部分。 熔丝部分可切割地设置成将电阻导电膜的一部分电连接到外部端子，或者将电阻性导电膜的一部分与外部端子电隔离。
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