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    Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing
    1.
    发明申请
    Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing 有权
    异步时钟分频器可降低时钟时序的片上变化

    公开(公告)号：US20130176060A1

    公开(公告)日：2013-07-11

    申请号：US12874627

    申请日：2010-09-02

    申请人： Raguram Modaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    发明人： Raguram Modaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    IPC分类号： H03K25/00

    CPC分类号： H03K25/00 ,  H03K23/42

    摘要： This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

    摘要翻译： 本发明是明确地确定在设计中使用的各种时钟沿的发生的一种手段，平衡集成电路内的各个位置处的时钟沿。 从外部源进入的时钟可能是片上变化（OCV）的来源，导致不可接受的时钟边缘偏移。 本发明将各种时钟分频器布置在使用这些时钟的远程位置的芯片上。 这最小化边缘发生的不确定性。

    Asynchronous clock dividers to reduce on-chip variations of clock timing
    2.
    发明授权
    Asynchronous clock dividers to reduce on-chip variations of clock timing 有权
    异步时钟分频器可减少片上时钟时钟变化

    公开(公告)号：US08970267B2

    公开(公告)日：2015-03-03

    申请号：US12874627

    申请日：2010-09-02

    申请人： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    发明人： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K23/42

    CPC分类号： H03K25/00 ,  H03K23/42

    摘要： This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

    摘要翻译： 本发明是明确地确定在设计中使用的各种时钟沿的发生的一种手段，平衡集成电路内的各个位置处的时钟沿。 从外部源进入的时钟可能是片上变化（OCV）的来源，导致不可接受的时钟边缘偏移。 本发明将各种时钟分频器布置在使用这些时钟的远程位置的芯片上。 这最小化边缘发生的不确定性。

    Clock control of pipelined memory for improved delay fault testing
    4.
    发明授权
    Clock control of pipelined memory for improved delay fault testing 有权
    流水线内存的时钟控制，用于改进延迟故障测试

    公开(公告)号：US08694843B2

    公开(公告)日：2014-04-08

    申请号：US13198324

    申请日：2011-08-04

    申请人： Ramakrishnan Venkatasubramanian ,  Sumant Kale ,  Abhijeet Ashok Chachad

    发明人： Ramakrishnan Venkatasubramanian ,  Sumant Kale ,  Abhijeet Ashok Chachad

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31858 ,  G06F11/24

    摘要： In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.

    摘要翻译： 在本发明的实施例中，通过将测试图案扫描成集成电路来测试流水线存储器组。 测试数据由测试图形形成并移入流水线存储体中的扫描链。 扫描链中的测试数据在第一个时钟周期内被发送到流水线存储器的输入端。 来自流水线存储体的输出的数据在第二周期的扫描输出链中捕获，其中第一和第二时钟周期之间的时间等于或大于存储体的读取等待时间。

    Clock Control of Pipelined Memory for Improved Delay Fault Testing
    6.
    发明申请
    Clock Control of Pipelined Memory for Improved Delay Fault Testing 有权
    用于改进延迟故障测试的流水线存储器的时钟控制

    公开(公告)号：US20130036337A1

    公开(公告)日：2013-02-07

    申请号：US13198324

    申请日：2011-08-04

    申请人： Ramakrishnan Venkatasubramanian ,  Sumant Kale ,  Abhijeet Ashok Chachad

    发明人： Ramakrishnan Venkatasubramanian ,  Sumant Kale ,  Abhijeet Ashok Chachad

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/31858 ,  G06F11/24

    摘要： In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.

    摘要翻译： 在本发明的实施例中，通过将测试图案扫描成集成电路来测试流水线存储器组。 测试数据由测试图形形成并移入流水线存储体中的扫描链。 扫描链中的测试数据在第一个时钟周期内被发送到流水线存储器的输入端。 来自流水线存储体的输出的数据在第二周期的扫描输出链中捕获，其中第一和第二时钟周期之间的时间等于或大于存储体的读取等待时间。