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    Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback
    5.
    发明授权
    Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback 有权
    具有异步读取和本地化反馈的输入流水线架构的多端口寄存器文件

    公开(公告)号：US08862836B2

    公开(公告)日：2014-10-14

    申请号：US13160174

    申请日：2011-06-14

    申请人： Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Naveen Bhoria

    发明人： Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Naveen Bhoria

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F5/00

    CPC分类号： G06F5/00 ,  G06F9/30141 ,  G11C8/12

    摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.

    摘要翻译： 在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。 由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。 当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。 在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。 来自流水线同步数据寄存器的哪些数据位被写入多端口寄存器文件由流水线同步位写入寄存器确定。 流水线同步位写入寄存器的输出选择存储多端口寄存器文件中寄存器中包含的多路复用器的哪些输入。

    Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback
    6.
    发明申请
    Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback 有权
    具有异步读取和本地化反馈的输入流水线结构的多端口寄存器文件

    公开(公告)号：US20120324175A1

    公开(公告)日：2012-12-20

    申请号：US13160174

    申请日：2011-06-14

    申请人： Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Naveen Bhoria

    发明人： Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Naveen Bhoria

    IPC分类号： G06F12/00

    CPC分类号： G06F5/00 ,  G06F9/30141 ,  G11C8/12

    摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.

    摘要翻译： 在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。 由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。 当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。 在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。 来自流水线同步数据寄存器的哪些数据位被写入多端口寄存器文件由流水线同步位写入寄存器确定。 流水线同步位写入寄存器的输出选择存储多端口寄存器文件中寄存器中包含的多路复用器的哪些输入。

    Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding
    10.
    发明申请
    Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding 有权
    具有输入流水线结构和异步读取数据转发的多端口寄存器文件

    公开(公告)号：US20120324174A1

    公开(公告)日：2012-12-20

    申请号：US13160156

    申请日：2011-06-14

    申请人： Raguram Damodaran ,  Ramakrishnan Vankatasubramanian ,  Naveen Bhoria

    发明人： Raguram Damodaran ,  Ramakrishnan Vankatasubramanian ,  Naveen Bhoria

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30141 ,  G06F5/06 ,  G06F9/3826

    摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.

    摘要翻译： 在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。 由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。 当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。 在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。 当读取地址与存储在流水线存储器中的写入地址相同时，存储在流水线同步数据寄存器中的数据的逐位AND运算结果和存储在流水线同步逐位寄存器中的数据显示在多路复用器的输出端 -port注册文件。