公开(公告)号：US07331005B2

公开(公告)日：2008-02-12

申请号：US11189231

申请日：2005-07-26

申请人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

发明人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

IPC分类号： G01R31/28 ,  G06K5/04 ,  G06F11/00

CPC分类号： G01R31/3016

摘要： Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

摘要翻译： 用于测试半导体器件的方法和装置。 测试接口被配置为与外部测试设备和被测设备（DUT）接口。 在一个实施例中，测试接口从外部测试装置接收测试数据和测试时钟信号。 测试数据根据测试时钟信号从测试接口输出到DUT。 此外，测试时钟信号被延迟一段时间，然后向设备发出延迟的时钟信号。 先前写入DUT的数据从DUT读出并与从外部测试装置接收的测试数据进行比较。 可以改变测试时钟信号被延迟的时间段以实现期望的时序。

公开(公告)号：US20060026475A1

公开(公告)日：2006-02-02

申请号：US11189231

申请日：2005-07-26

申请人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

发明人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

IPC分类号： G01R31/28

CPC分类号： G01R31/3016

摘要： Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

摘要翻译： 用于测试半导体器件的方法和装置。 测试接口被配置为与外部测试设备和被测设备（DUT）接口。 在一个实施例中，测试接口从外部测试装置接收测试数据和测试时钟信号。 测试数据根据测试时钟信号从测试接口输出到DUT。 此外，测试时钟信号被延迟一段时间，然后向设备发出延迟的时钟信号。 先前写入DUT的数据从DUT读出并与从外部测试装置接收的测试数据进行比较。 可以改变测试时钟信号被延迟的时间段以实现期望的时序。

公开(公告)号：US07211451B2

公开(公告)日：2007-05-01

申请号：US10298772

申请日：2002-11-18

申请人： Thorsten Meyer ,  Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez ,  Roland Irsigler

发明人： Thorsten Meyer ,  Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez ,  Roland Irsigler

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L23/28 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L21/67121 ,  H01L21/67132 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/3128 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/92 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2224/96 ,  H01L2224/82

摘要： A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

摘要翻译： 一种用于制造组件模块的方法，所述组件模块包括模块载体和在其上形成接触的多个部件，包括以下步骤：以预定的接触特定间隔将表面粘合膜上的分离的组分布置在彼此之间， 将部件嵌入柔性材料中以形成保持部件的柔性保持框架，拉出膜，在部件的暴露侧上产生接触形成元件，执行部件的功能测试，并且如果需要， 修理和/或更换部件，以及固定和保持在模块架上的保持框架中保持的部件。

公开(公告)号：US20060262614A1

公开(公告)日：2006-11-23

申请号：US11415443

申请日：2006-05-01

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.

摘要翻译： 提供了一种集成电路，该集成电路具有用于根据测试模式从集成电路读出错误数据的测试电路，其中该误差数据经由第一和第二数据输出被输出，并且其中一个地址和 读取命令被应用于集成电路，以通过数据输出之一读出与地址相关联的错误数据。 测试电路被配置成使得当应用第一读取命令时，测试电路在第一数据输出处输出误差数据并将第二数据输出切换为高阻抗，并且当应用第二读取命令时， 测试电路在第二个数据输出端输出误差数据，并将第一个数据输出切换到高阻抗。

公开(公告)号：US20050017748A1

公开(公告)日：2005-01-27

申请号：US10865050

申请日：2004-06-10

申请人： Frank Weber ,  Gerd Frankowsky

发明人： Frank Weber ,  Gerd Frankowsky

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2863 ,  G01R31/2889

摘要： Test system for testing integrated chips and an adapter element for a test system. One embodiment provides a test system for testing integrated chips in a burn-in test operation, the integrated chips to be tested being arranged in groups on a burn-in board, the burn-in board having a first connecting device in order to connect the burn-in board to a tester device, the tester device comprising a test module with a test circuit in order to test chips on the burn-in board in accordance with the burn-in test operation, the test module having a second connecting device in order to connect the burn-in board to the test module via the second connecting device, a plurality of test modules being provided, the second connecting devices of which can be contact-connected to a plurality of third connecting devices of an adapter element, the adapter element having a fourth connecting device for contact-connection of the first connecting device of the burn-in board, the third connecting devices of the adapter element being connected to the fourth connecting device in such a way that, in the contact-connected state, it is possible to test each integrated circuit of a group with one of the test modules.

摘要翻译： 用于测试集成芯片的测试系统和用于测试系统的适配器元件。 一个实施例提供了一种用于在老化测试操作中测试集成芯片的测试系统，待测试的集成芯片分组放置在老化板上，该老化板具有第一连接设备，以便连接 所述测试装置包括具有测试电路的测试模块，以便根据所述老化测试操作在所述老化板上测试芯片，所述测试模块具有第二连接装置， 为了通过第二连接装置将老化板连接到测试模块，提供了多个测试模块，其中第二连接装置可以与适配器元件的多个第三连接装置接触连接， 适配器元件具有用于接合连接老化板的第一连接装置的第四连接装置，适配器元件的第三连接装置以这样的方式连接到第四连接装置 在接触连接状态下，可以用一个测试模块来测试组中的每个集成电路。

公开(公告)号：US06707746B2

公开(公告)日：2004-03-16

申请号：US10210628

申请日：2002-07-31

申请人： Gerd Frankowsky ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Barbara Vasquez

IPC分类号： G11C700

CPC分类号： G11C7/1045 ,  G11C2207/105 ,  G11C2207/2254

摘要： Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ “enable” latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.

摘要翻译： 公开了使用熔断器和反熔丝锁存器（62）进行封装后选择输入/输出通道数（98,109）的电路。 各种实施例允许传统的接合焊盘（14,16,18）用于在封装之前的输入/输出通道的数量的初始选择。 然而，通过提供不同的选择信号（52,54），输入/输出通道的数量可以由用户在封装之后的任何时间改变。 其他实施例使用“使能”锁存电路（133,135）允许用户在封装之后的任何时间进行初始选择，然后进行至少一个以后的选择。

公开(公告)号：US06651203B1

公开(公告)日：2003-11-18

申请号：US09312974

申请日：1999-05-17

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R3128

CPC分类号： G11C29/36 ,  G06F11/2635

摘要： A semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data provided on input/output pins, and a pattern generator formed on the memory chip. The pattern generator further includes a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array. An addressing circuit for accessing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array is included.

摘要翻译： 根据本发明的半导体存储器芯片包括待测试的第一存储器阵列，其包括以行和列排列的多个存储单元，存储单元通过采用位线和字线被访问以读取和写入数据，所提供的数据 在输入/输出引脚上，以及形成在存储芯片上的图形发生器。 图案生成器还包括包括多个存储体的可编程存储器阵列，存储体具有以行和列排列的存储单元，每个存储体能够存储要为每个输入/输出引脚产生的模式的数据 第一个存储器阵列。 包括用于访问存储在可编程存储器阵列中的数据以寻址要发送到第一存储器阵列和从第一存储器阵列传送的各个数据的寻址电路。

公开(公告)号：US06603694B1

公开(公告)日：2003-08-05

申请号：US10068789

申请日：2002-02-05

申请人： Gerd Frankowsky ,  Gunther Lehmann

发明人： Gerd Frankowsky ,  Gunther Lehmann

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.

摘要翻译： 提供了用于刷新存储在动态存储单元阵列中的数据的电路。 该电路包括集成电路芯片。 芯片具有形成在其上的存储单元阵列。 该电路还包括用于确定每个存储器单元中的数据保持时间的刷新率分析电路，以及这些确定刷新地址修改信号。 还提供了一种刷新地址生成器，其形成在芯片上并由芯片外部产生的刷新命令信号和地址修改信号馈送。 刷新地址生成器向内存单元阵列提供内部刷新命令以及刷新地址。 小区具有响应于这种内部刷新命令刷新的数据。 刷新率分析电路确定具有小于预定值的数据保留时间的阵列中的单元。

公开(公告)号：US20090039910A1

公开(公告)日：2009-02-12

申请号：US12174302

申请日：2008-07-16

申请人： Gerd Frankowsky ,  Roman Mayr

发明人： Gerd Frankowsky ,  Roman Mayr

IPC分类号： G01R1/073

CPC分类号： G01R31/2893 ,  G01R31/2889

摘要： A test apparatus for semiconductor modules. One embodiment provides a test system. The test system includes a handler configured to receive at least one semiconductor module. The test system is equipped with a plurality of different pin cards. The handler has at least two independent groups of test receptacles.

摘要翻译： 一种用于半导体模块的测试装置。 一个实施例提供一种测试系统。 测试系统包括配置成接收至少一个半导体模块的处理器。 测试系统配备有多个不同的针卡。 处理器至少有两组独立的测试插座。

公开(公告)号：US07437627B2

公开(公告)日：2008-10-14

申请号：US10784134

申请日：2004-02-20

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/72 ,  G11C29/44 ,  G11C29/56 ,  G11C2029/5606

摘要： Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, wherein defect addresses, the address values of which specify the defective memory areas of the memory module, are generated from addresses of the memory areas and the associated defect data, the defect addresses being stored in the test system, the repair solution being determined from the stored defect addresses.

摘要翻译： 用于确定测试系统中的存储器模块的修复解决方案的方法，连续地测试存储器模块的存储区域，以便为每个存储器区域获得指定相应存储器区域是否有缺陷的缺陷数据，其中缺陷地址 ，其地址值指定存储器模块的缺陷存储区域，是从存储区域和相关联的缺陷数据的地址生成的，缺陷地址存储在测试系统中，修复解决方案根据存储的缺陷地址确定 。