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    TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES
    7.
    发明申请
    TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES 有权
    通过增强蚀刻控制策略形成上述晶体管上的不同应力层的技术

    公开(公告)号：US20080206905A1

    公开(公告)日：2008-08-28

    申请号：US11868789

    申请日：2007-10-08

    申请人： Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

    发明人： Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

    IPC分类号： H01L21/66

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L22/26 ,  H01L29/7843

    摘要： During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

    摘要翻译： 在具有不同类型的固有应力的应力层的图案化期间，可以通过基于表示第二和第二电介质层的光学测量数据的受控蚀刻来显着地减少基于二氧化硅的蚀刻指示剂材料沉积的影响 蚀刻速率，因此，各个蚀刻工艺的性能。 在其他情况下，可以将高效的蚀刻指示剂物质结合到应力介电层中，或者可以在其表面部分上形成具有减小的层厚度，从而提供增强的端点检测信号，而不产生基于二氧化硅的指示剂层的负面影响。 在一个说明性实施例中，应力硅，氮和碳的层可以与应力硅和含氮层组合，其中碳类提供突出的端点检测信号。

    Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies
    9.
    发明授权
    Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies 有权
    通过增强的蚀刻控制策略对形成在晶体管上方的不同应力层进行图案化的技术

    公开(公告)号：US07883629B2

    公开(公告)日：2011-02-08

    申请号：US11868789

    申请日：2007-10-08

    申请人： Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

    发明人： Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

    IPC分类号： C03C15/00 ,  G01R31/00 ,  H01L21/00 ,  H01L21/66

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L22/26 ,  H01L29/7843

    摘要： During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

    摘要翻译： 在具有不同类型的固有应力的应力层的图案化期间，可以通过基于表示第二和第二电介质层的光学测量数据的受控蚀刻来显着地减少基于二氧化硅的蚀刻指示剂材料沉积的影响 蚀刻速率，因此，各个蚀刻工艺的性能。 在其他情况下，可以将高效的蚀刻指示剂物质结合到应力介电层中，或者可以在其表面部分上形成具有减小的层厚度，从而提供增强的端点检测信号，而不产生基于二氧化硅的指示剂层的负面影响。 在一个说明性实施例中，应力硅，氮和碳的层可以与应力硅和含氮层组合，其中碳类提供突出的端点检测信号。