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    Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes
    1.
    发明授权
    Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
    使用产品选择代码为集成电路系列提供类似模具的方法部分禁用

    公开(公告)号：US07402443B1

    公开(公告)日：2008-07-22

    申请号：US11333819

    申请日：2006-01-17

    申请人： Raymond C. Pang ,  Trevor J. Bauer ,  F. Erich Goetting ,  Bruce E. Talley ,  Steven P. Young

    发明人： Raymond C. Pang ,  Trevor J. Bauer ,  F. Erich Goetting ,  Bruce E. Talley ,  Steven P. Young

    IPC分类号： G01R31/26

    CPC分类号： H01L27/11807 ,  H01L27/0207

    摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.

    摘要翻译： 提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。 第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。 第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。 第三IC管芯基本上类似于第一管芯的第一部分。 第二和第三包可以是相同的，并且包装的模具可以在系统中互换。 当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

    Block RAM with reset to user selected value
    2.
    发明授权
    Block RAM with reset to user selected value 有权
    将RAM重置为用户选择的值

    公开(公告)号：US06282127B1

    公开(公告)日：2001-08-28

    申请号：US09625672

    申请日：2000-07-24

    申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    IPC分类号： G11C700

    CPC分类号： G11C7/1051 ,  G11C7/1057

    摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.

    摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。 复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。 当RAM块被配置为状态机时，这是有用的。 因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。 当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。

    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
    3.
    发明授权
    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
    多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路

    公开(公告)号：US07345507B1

    公开(公告)日：2008-03-18

    申请号：US11333991

    申请日：2006-01-17

    申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

    摘要翻译： 多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 选择码存储电路存储产品选择码。 产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。 产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。 选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。 产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

    Circuit for and method of implementing a content addressable memory in a programmable logic device
    4.
    发明授权
    Circuit for and method of implementing a content addressable memory in a programmable logic device 有权
    在可编程逻辑器件中实现内容可寻址存储器的电路和方法

    公开(公告)号：US07248491B1

    公开(公告)日：2007-07-24

    申请号：US11044746

    申请日：2005-01-26

    申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C7/1075

    摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

    摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

    Memory device and method of transferring data in memory device
    6.
    发明授权
    Memory device and method of transferring data in memory device 有权
    存储器件和在存储器件中传送数据的方法

    公开(公告)号：US07242633B1

    公开(公告)日：2007-07-10

    申请号：US11044740

    申请日：2005-01-26

    申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    IPC分类号： G11C8/00

    CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00

    摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

    摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

    Block RAM with configurable data width and parity for use in a field programmable gate array
    7.
    发明授权
    Block RAM with configurable data width and parity for use in a field programmable gate array 有权
    块RAM具有可配置的数据宽度和奇偶校验，用于现场可编程门阵列

    公开(公告)号：US06346825B1

    公开(公告)日：2002-02-12

    申请号：US09680205

    申请日：2000-10-06

    申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    IPC分类号： H03K19177

    CPC分类号： H03K19/1776

    摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.

    摘要翻译： 为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。 块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。 在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。 响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。 在配置PLD期间对配置位进行编程。 在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。 在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。 在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

    Block RAM having multiple configurable write modes for use in a field programmable gate array
    8.
    发明授权
    Block RAM having multiple configurable write modes for use in a field programmable gate array 有权
    具有用于现场可编程门阵列的多个可配置写模式的块RAM

    公开(公告)号：US06373779B1

    公开(公告)日：2002-04-16

    申请号：US09574300

    申请日：2000-05-19

    申请人： Raymond C. Pang ,  Steven P. Young

    发明人： Raymond C. Pang ,  Steven P. Young

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16

    摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.

    摘要翻译： 为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。 块RAM包括存储单元阵列和可配置为选择用于访问存储单元阵列的多个写入模式之一的控制逻辑。 在一个实施例中，写入模式包括具有回写模式的写入，不具有回写模式的写入以及读取和写入模式。 响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择写入模式。 在配置PLD期间对配置位进行编程。 在一个变化中，控制逻辑响应于用户信号选择写入模式。 在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。 在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）写入模式。 第一和第二端口的宽度也可以独立地配置。

    Circuits for shifting bussed data
    9.
    发明授权
    Circuits for shifting bussed data 有权
    用于转换总线数据的电路

    公开(公告)号：US09002915B1

    公开(公告)日：2015-04-07

    申请号：US12417048

    申请日：2009-04-02

    申请人： Steven P. Young ,  Brian C. Gaide

    发明人： Steven P. Young ,  Brian C. Gaide

    IPC分类号： G06F7/00 ,  G06F15/00 ,  G06F5/01

    CPC分类号： G06F5/015 ,  H03K19/17736

    摘要： A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.

    摘要翻译： 用于移位总线数据的电路包括第一列移位块，比较块和第二列复用器块。 第一列将总线数据移位由移位控制输入的第一位指定的位数。 比较块确定移位控制输入的第二位的值，并创建反映该值的输出。 第二列具有耦合到比较块的输出的控制输入，当移位控制输入的第二位具有第一值时将数据移位一个字节，并且当第二位具有第二值时不移位数据 。 移位，比较和多路复用器块可以是基本相似的可编程以执行这些功能的逻辑块，可以包括N位数据输入和输出，并且可以作为N位总线对总线数据进行操作。

    Clock distribution to facilitate gated clocks
    10.
    发明授权
    Clock distribution to facilitate gated clocks 有权
    时钟分配方便门控时钟

    公开(公告)号：US08058905B1

    公开(公告)日：2011-11-15

    申请号：US12363722

    申请日：2009-01-31

    申请人： Matthew H. Klein ,  Richard W. Swanson ,  Trevor J. Bauer ,  Steven P. Young ,  Andy DeBaets

    发明人： Matthew H. Klein ,  Richard W. Swanson ,  Trevor J. Bauer ,  Steven P. Young ,  Andy DeBaets

    IPC分类号： H03K19/00 ,  H03K3/356

    CPC分类号： G06F1/10 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

    摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.

    摘要翻译： 描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。 通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。 门控时钟电路通过使能信号为时钟元件提供门控时钟信号。 包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。 时钟信号通过时钟分配网络分发给CLB。 对应于一些时钟信号提供时钟使能信号。 在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。 通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。