公开(公告)号：US20180301552A1

公开(公告)日：2018-10-18

申请号：US16008590

申请日：2018-06-14

Applicant: Renesas Electronics Corporation

Inventor： Toshiharu NAGUMO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.

公开(公告)号：US20140252483A1

公开(公告)日：2014-09-11

申请号：US14204371

申请日：2014-03-11

Applicant: Renesas Electronics Corporation

Inventor： Toshiharu NAGUMO

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/845

Abstract: A semiconductor device and method making it comprises pFETs with an SiGe channel and nFETs with an Si channel, formed on an SOI substrate. Improved uniformity of fin height and width is attained by forming the fins additively by depositing an SiGe layer on the SOI substrate and forming first fins from the superposed SiGe layer and underlying thin Si film of the SOI substrate. Second fins of Si can then be formed by replacing the upper SiGe portions of selected first fins with Si.

Abstract translation: 制造它的半导体器件和方法包括形成在SOI衬底上的具有SiGe沟道的pFET和具有Si沟道的nFET。 通过在SOI衬底上沉积SiGe层并且从SOI衬底的叠加的SiGe层和下面的薄Si膜形成第一鳍片来附加地形成散热片高度和宽度来提高翅片高度和宽度的均匀性。 然后可以通过用Si代替所选择的第一散热片的上部SiGe部分来形成Si的第二散热片。

公开(公告)号：US20140239399A1

公开(公告)日：2014-08-28

申请号：US14188835

申请日：2014-02-25

Applicant: Renesas Electronics Corporation

Inventor： Toshiharu NAGUMO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.

Abstract translation: 一种使其利用包括第一半导体材料的芯和第二半导体材料的外延覆层的三维沟道区的半导体器件和方法。 第一和第二半导体材料分别具有不同的晶格常数，从而在外延覆层中产生应变。 这些器件通过栅极最后工艺形成，使得仅在执行高温处理之后才沉积第二半导体材料。 因此，晶格应变基本上不松弛，并且不影响晶格应变通道区域的改进的性能优点。

公开(公告)号：US20160079426A1

公开(公告)日：2016-03-17

申请号：US14952782

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Hiroshi TAKEDA ,  Toshiharu NAGUMO ,  Takashi HASE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

公开(公告)号：US20160056207A1

公开(公告)日：2016-02-25

申请号：US14809106

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiharu NAGUMO ,  Kiyoshi TAKEUCHI ,  Toyoji YAMAMOTO

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/16

Abstract: Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.

Abstract translation: 公开了减少ReRAM中晶体管面积的半导体器件。 在位线和板线的组合中，多个存储单元彼此不同。 板线PL2的电位为成形电压。 相反，其他板条的电位为+ Vi。 位线BL2的电位为0V（地电位）。 相反，其他位线的电位为+ Vi。 是+ Vgf的潜力。 相反，其他字线的电位为+ Vi。

公开(公告)号：US20160027872A1

公开(公告)日：2016-01-28

申请号：US14873581

申请日：2015-10-02

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro HIRAI ,  Toshiharu NAGUMO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/45 ,  H01L29/16 ,  H01L29/161 ,  H01L21/306 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/30604 ,  H01L29/0611 ,  H01L29/1087 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device, includes a substrate, a source structure and a drain structure formed on the substrate. At least one interconnect structure interconnects the source structure and the drain structure and serves as a channel therebetween. A gate structure is formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel. Each of the interconnect structures include a center core serving as a backbias electrode for the channel.

Abstract translation: 一种半导体器件，包括形成在衬底上的衬底，源极结构和漏极结构。 至少一个互连结构将源结构和漏极结构互连，并且用作它们之间的通道。 栅极结构形成在至少一个互连结构上，以提供沟道中载流子的导电性的控制。 每个互连结构包括用作沟道的反向电极的中心芯。

公开(公告)号：US20140183452A1

公开(公告)日：2014-07-03

申请号：US14134747

申请日：2013-12-19

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro HIRAI ,  Toshiharu NAGUMO

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/30604 ,  H01L29/0611 ,  H01L29/1087 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween. A gate structure is formed over said at least one nanowire structure to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel.

Abstract translation: 半导体器件包括衬底和形成在衬底上的源极结构和漏极结构。 至少一个纳米线结构互连了源结构和漏极结构，并且用作它们之间的通道。 在所述至少一个纳米线结构上形成栅极结构以提供沟道中载流子的导电性的控制，并且纳米线结构包括用作沟道的反向电极的中心芯。