-
公开(公告)号：US3944984A
公开(公告)日：1976-03-16
申请号：US463281
申请日：1974-04-23
CPC分类号： G06F9/24 , G05B19/056 , G05B2219/13013 , G05B2219/13128 , G05B2219/13142 , G05B2219/15048
摘要： A miniaturized computer controller system utilizes reprogrammable "read only" ultraviolet memory chips instead of conventional core memories to store a control program comprising variable information regarding all electrical elements in all electrical circuit lines of the controller. The memory chips are reprogrammable within the controller and thus delicate removal of the chips for reprogramming is eliminated. The controller utilizes a central processor removably interfitting with a reprogramming module that also communicates with a programming panel.When in a "monitor" mode, the programming panel, in conjunction with the reprogramming module, allows the operator to view any particular electrical circuit line while the controller is operating. A scroll switch on the programming panel further allows the operator to view sequentially higher or lower numbered electrical circuit lines while a trace switch provides for examining any electrical circuit line to which a currently viewed element is referenced.When in a " program" mode, the programming panel, in combination with the reprogramming module, replaces the variable memory "read only" chips and allows the controller to continue operation while the operator is programming, adjusting, or de-bugging the electrical circuit lines. Following the programming of the electrical circuit lines with the desired electrical elements, the information regarding these lines is transferred to the reprogrammable "read only" memory chips when the programming panel is in a "write" mode. In this mode all the information previously stored in the memory chips is first erased by ultraviolet light, followed by the insertion of the new information regarding the electrical circuit lines.Following the transferral of information to the memory chips, the reprogramming module is disconnected from the central processor and replaced by a removably interfitting power supply module, whereby the system operates with electrical circuit line information stored in the reprogrammable memory chips.
摘要翻译： 微型计算机控制器系统利用可再编程的“只读”紫外线存储器芯片，而不是传统的核心存储器来存储包括关于控制器的所有电路线中的所有电气元件的可变信息的控制程序。 存储器芯片在控制器内可重新编程，因此消除了用于重新编程的芯片的精细去除。 控制器利用中央处理器与可编程面板进行通信的可重新编程模块进行可拆卸的配合。
-
2.发明授权Realtime systolic, multiple-instruction, single-data parallel computer system 失效实时收缩，多指令，单数据并行计算机系统
公开(公告)号：US5136717A
公开(公告)日：1992-08-04
申请号：US276413
申请日：1988-11-23
IPC分类号： G06F15/16 , G06F9/44 , G06F15/167 , G06F15/80 , G06N5/04
CPC分类号： G06F15/167 , G06F15/8015
摘要： A computer system especially for solution of real time inference problems is disclosed. The system includes a systolic cellular processor which provides predictable and responsive real time operation and fine grain programmability. The system comprises a plurality of separate processor cells each having its own local memory, the cells running simultaneously and operative to execute their respective program instructions. A global memory is coupled via a global bus to the processor cells and provides data to the cells and stores data from the cells. The bus provides effectively simultaneous access of all cells to the global memory. A further feature of the system is a novel parallel programming language using English syntax and which provides synchronous and predictable binding of code to each cell. A graphic work station is provided as a user interface to provide visual access to each cell or to cell groups for ease of control. The system can also function to emulate large scale integrated circuit processors by reason of the fine grain programmed operation of the system.
摘要翻译： 公开了一种特别用于解决实时推理问题的计算机系统。 该系统包括收缩细胞处理器，其提供可预测和响应的实时操作和细粒度可编程性。 该系统包括多个单独的处理器单元，每个单独的处理器单元具有其自己的本地存储器，该单元同时运行并且可操作以执行它们各自的程 全局存储器通过全局总线耦合到处理器单元，并向单元提供数据并存储来自单元的数据。 总线有效地同时访问所有单元到全局存储器。 该系统的另一个特征是使用英语语法的新颖的并行编程语言，并且提供了代码到每个单元的同步和可预测的绑定。 提供图形工作站作为用户界面，以提供对每个单元或单元组的可视访问以便于控制。 该系统还可以通过系统的细粒度编程操作来模拟大规模集成电路处理器。
-
公开(公告)号：US06739078B2
公开(公告)日：2004-05-25
申请号：US10216056
申请日：2002-08-09
IPC分类号： G02F502
CPC分类号： B25J9/1656 , E02F3/435 , E02F9/2045 , E02F9/205 , G05B2219/31241 , G05B2219/33192 , G05B2219/34279 , G05B2219/36169 , G05B2219/40099 , G05B2219/45012
摘要： A system to control a piece of construction equipment or other piece of heavy equipment at a remote location via a data network in which a user provides movement instructions via a graphical user interface at a user PC to a programmable controller interfaced to the data network and the hydraulic movement systems of the heavy equipment. The graphical user interface includes a visual representation portion and a user control portion. A visual representation of the moveable elements of the heavy equipment is provided to the user via the graphical user interface, and the user inputs movement instructions via the user control portion of the graphical user interface.
摘要翻译： 一种用于经由数据网络在远程位置控制一块建筑设备或其他重型设备的系统，其中用户通过用户PC上的图形用户界面向连接到数据网络的可编程控制器提供移动指令， 液压机械系统的重型设备。 图形用户界面包括可视表示部分和用户控制部分。 通过图形用户界面向用户提供重型设备的可移动元件的视觉表示，并且用户经由图形用户界面的用户控制部分输入移动指令。
-
公开(公告)号：US4979074A
公开(公告)日：1990-12-18
申请号：US364892
申请日：1989-06-12
申请人： Richard E. Morley , David A. Baker
发明人： Richard E. Morley , David A. Baker
CPC分类号： H05K7/20509 , H05K3/0061 , H05K2201/0133 , H05K2201/10598 , H05K3/3447
摘要： A heat sink for a printed circuit board in comprised of a thermally-conductive plate having on one surface a thermally-conductive, electrically-insulative elastomer layer which conformally engages at leasts a portion of the back surface of the printed circuit board. The ends of pins of electronic components mounted on the board and desired to be cooled embed into the elastomer layer to provide a conductive path for transfer of heat from the electronic components to the elastomer layer and then to the thermally-conductive plate.
摘要翻译： 一种用于印刷电路板的散热器，其由导热板组成，该导热板在一个表面上具有导热的电绝缘弹性体层，其至少与印刷电路板的后表面的一部分共形接合。 安装在板上并希望被冷却的电子部件的引脚的端部嵌入到弹性体层中，以提供用于将热量从电子部件传递到弹性体层然后传导到导热板的导电路径。
-
公开(公告)号：US4648064A
公开(公告)日：1987-03-03
申请号：US879200
申请日：1978-02-21
申请人： Richard E. Morley
发明人： Richard E. Morley
CPC分类号： G05B19/054 , G06F13/38 , G05B2219/1188 , G05B2219/13004 , G05B2219/13142 , G05B2219/15018 , G05B2219/15026
摘要： A parallel process controller capable of expandable, parallel operating multi-function control of processes without degradation of performance. The process controller comprises up to N (where N is a positive integer) programmable command memory modules, and also comprises data memory modules, an input/output system, a high speed data bus (N-bus) and a general timing and control unit. Each command memory module performs the functional equivalent of a central processing unit with storage of instruction lines designatable by a user via a programming panel. Each command memory module operates autonomously, without regard to the other command memory modules and cyclically solves each of the user instruction lines in a short, fixed length of time. Each data memory module supplements data storage in the command memory modules. The N-bus is a high speed data bus that cyclically interconnects for a fixed length of time each command memory module during one of N control signals generated by the general timing and control unit, to any of the data memory modules and to the input/output system. During this length of time, the selected command memory module may address, read, or write in any location in any data memory module. An interconnectable programming panel may monitor, program, or control line status indicators for any instruction line within any command module or any line within any data memory module. The programming panel communicates with the controller via a dedicated channel of the input/output system.
摘要翻译： 一种并行过程控制器，能够进行可扩展的，并行的多功能控制过程，而不会降低性能。 过程控制器包括最多N个（其中N是正整数）可编程命令存储器模块，并且还包括数据存储器模块，输入/输出系统，高速数据总线（N总线）和通用定时和控制单元 。 每个命令存储器模块通过编程面板执行用户可指定的指令行的存储的中央处理单元的功能等效。 每个命令存储器模块自动操作，而不考虑其他命令存储器模块，并且以短的固定长度周期性地解决每个用户指令行。 每个数据存储器模块补充命令存储器模块中的数据存储。 N总线是一种高速数据总线，其在由一般定时和控制单元产生的N个控制信号之一期间，将每个命令存储器模块的固定长度周期性地互连到任何数据存储器模块和输入/ 输出系统。 在这段时间内，所选择的命令存储器模块可以在任何数据存储器模块中的任何位置进行寻址，读取或写入。 可互连编程面板可以监视，编程或控制任何指令模块内任何指令行或任何数据存储器模块内的任何行的线路状态指示器。 编程面板通过输入/输出系统的专用通道与控制器进行通信。
-
公开(公告)号：US4506362A
公开(公告)日：1985-03-19
申请号：US401974
申请日：1982-07-26
申请人： Richard E. Morley
发明人： Richard E. Morley
CPC分类号： G06F11/106 , G06F11/1024 , G06F11/2205
摘要： A systematic data memory error detection and correction apparatus periodically reads data from each addressable memory location, determines the presence or absence of an error in the addressed data memory location and, if an error is detected, corrects the error and writes the corrected data back into the addressed memory location. The apparatus may include circuitry for logging those areas of the data memory where errors have been detected, such logging showing either the address location where an error is detected or alternatively indicating the repetitiveness of an error at any particular addressed memory location. Such data logging facilitates determination of hardware or "hard" type errors as distinguished from non-hardware or "soft" type errors. The latter type errors are typically found in dynamic random access memories (dynamic RAM's) which occasionally and randomly have errors due to bombardment of cosmic energy and alpha particles, the latter typically due to minute radioactive elements in silicon materials used in the fabrication of such memories. When the present apparatus is used in conjunction with dynamic RAM's, the error detection and correction is typically performed during "refresh" times which are necessary for maintaining proper stored charge in such devices. By so doing, the access performance of the memory is not degraded by the error detection and correction apparatus.
摘要翻译： 系统数据存储器错误检测和校正装置周期性地从每个可寻址存储器位置读取数据，确定所寻址的数据存储器位置中存在或不存在错误，并且如果检测到错误，则校正错误并将校正后的数据写回 寻址的存储器位置。 该装置可以包括用于记录已经检测到错误的数据存储器的那些区域的电路，这样的记录显示检测到错误的地址位置或者替代地指示在任何特定寻址的存储器位置处的错误的重复性。 这样的数据记录有助于确定与非硬件或“软”类型错误不同的硬件或“硬”类型错误。 后一种类型的错误通常发生在动态随机存取存储器（动态RAM）中，其随机地由于宇宙能量和α粒子的轰击而产生错误，后者通常是由于用于制造这种存储器的硅材料中的微小的放射性元素 。 当本装置与动态RAM一起使用时，通常在“刷新”时间期间执行错误检测和校正，这对于在这种装置中维持适当的存储电荷是必需的。 通过这样做，存储器的访问性能不会被错误检测和校正装置降级。
-
7.发明授权Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same 失效使用智能复合存储器和输入/输出模块的具有多处理器能力的数字计算机及其执行方法
公开(公告)号：US4276594A
公开(公告)日：1981-06-30
申请号：US916274
申请日：1978-06-16
申请人： Richard E. Morley
发明人： Richard E. Morley
CPC分类号： G06F13/124 , G06F13/18 , G06F13/287 , G06F15/167
摘要： A digital computer with the capability of incorporating multiple central processing units (CPU's), utilizes an address and data bus between each central processing unit and from one to fifteen intelligent composite memory and input/output modules (MIO). Data is transferred to and from each MIO and the CPU synchronously by a bus during one phase of a three phase clocking cycle. During a second phase of the clocking cycle data on one or more low speed serial data channels within each MIO is transferred to and from the MIO and external devices. During the third phase of the clocking cycle data on a high speed direct memory access channel (DMA) is transferred to and from the MIO and one or more external devices. Additional CPU's can be interconnected with the first CPU by means of an inter-processor buffer module (IPB) which interconnects to the bus at one end and the additional CPU, by means of a bus, at its other end. The IPB may be a software modifiable MIO and can store data addressable by the two interconnected CPU's. In turn, the additional CPU and its associated bus interconnects by the second bus with from one to fifteen additional MIO's or IPB's, allowing cascading of CPU's and associated MIO's and IPB's. Since all data transfers to and from the MIO's and external devices occur at time phases separate from the first time phase in which the CPU communicates with the MIO's and IPB's, the computational speed of any CPU is independent of the quantity of data transferred between the MIO's and IPB's and associated external devices or additional CPU's.
摘要翻译： 具有并入多个中央处理单元（CPU）的能力的数字计算机利用每个中央处理单元与1至15个智能复合存储器和输入/输出模块（MIO）之间的地址和数据总线。 在三相时钟周期的一个阶段，数据通过总线同步传输到每个MIO和CPU。 在时钟周期的第二阶段期间，每个MIO内的一个或多个低速串行数据信道上的数据被传送到MIO和外部设备。 在时钟周期的第三阶段期间，高速直接存储器存取通道（DMA）上的数据被传送到MIO和一个或多个外部设备。 附加的CPU可以通过处理器间缓冲模块（IPB）与第一个CPU互连，该模块在另一端通过总线与一端的总线和附加的CPU相互连接。 IPB可以是可修改软件的MIO，并且可以存储由两个互连的CPU可寻址的数据。 反过来，额外的CPU及其相关的总线互连由第二总线与一到十五个额外的MIO或IPB，允许CPU和相关的MIO和IPB的级联。 由于所有传输到MIO和外部设备的数据都是在与CPU与MIO和IPB通信的第一阶段分开的时间段发生的，因此任何CPU的计算速度都与MIO的传输数据量无关 和IPB及其相关的外部设备或附加的CPU。
-
公开(公告)号：US4007443A
公开(公告)日：1977-02-08
申请号：US467283
申请日：1974-05-06
CPC分类号： H03M11/18 , G06F3/0235 , G06F3/0489 , Y10S379/906
摘要： An interactive terminal which is capable of complete hand-held operation with total freedom of position and location is provided. The terminal incorporates a self contained full 128-character keyboard, a 20-character alphanumeric readout, and a 1000-character memory. The terminal allows the generation of all 128 ASCII characters plus "break." In order to assure review of any message, a conveniently positioned scroll switch is incorporated to advance or roll back any messsage in the memory for presentation on the display.When previous messages are displayed and incoming information is being received by the terminal, the light intensity of the displayed messages modulates to indicate to the operator that information is being received but not displayed. The unique, totally portable, hand-held interactive terminal is provided with a 20 key keyboard which is operated with one hand, while the other hand selects one of four different information levels for each key. Consequently, each of the 20 keys is capable of transmitting four different characters or other information thereby assuring easy, compact transmission of all numeric, alphabetic, and punctuation characters, and command information to an interconnected device.The interactive computer terminal prevents the transmission of information when more than one of the twenty keys of the keyboard is depressed simultaneously In addition, the terminal allows for the automatic transmission of any characters when the corresponding key is depressed for a short period of time. Furthermore, an audible alarm is incorporated which automatically sounds when improper keyboard operation is attempted.The interactive terminal provides for local operation that allows the invention to display information without transmitting this information to any interconnected device. The display of the present terminal incorporates a cursor that indicates the position, type and information level of the next character to be generated and transmitted if a keyboard key is depressed.Furthermore, the interactive terminal provides for the selection of various parameters; including communication speed, parity, half-duplex or full-duplex mode, upper or lower case alphanumeric transmission from the keyboard, and a "justify" operation for presenting of words on more than one line if these words are equal to or less than 10 characters.
摘要翻译： 提供了能够完全实现手持操作的交互式终端，具有完全自由的位置和位置。 终端包含一个自包含的全128个字符的键盘，一个20个字符的字母数字读出和一个1000字符的内存。 终端允许生成所有128个ASCII字符加“断点”。 为了确保检查任何消息，结合了方便定位的滚动开关，以推进或回滚存储器中的任何消息以便呈现在显示器上。
-
公开(公告)号：US5418952A
公开(公告)日：1995-05-23
申请号：US897361
申请日：1992-06-11
IPC分类号： G06F15/16 , G06F9/44 , G06F15/167 , G06F15/80 , G06N5/04 , G06F13/362
CPC分类号： G06F15/167 , G06F15/8015
摘要： A computer system especially for solution of real time inference problems is disclosed. The system includes a systolic cellular processor which provides predictable and responsive real time operation and fine grain programmability. The system comprises a plurality of separate processor cells each having its own local memory, the cells running simultaneously and operative to execute their respective program instructions. A global memory is coupled via a global bus to the processor cells and provides data to the cells and stores data from the cells. The bus provides effectively simultaneous access of all cells to the global memory. A further feature of the system is a novel parallel programming language using English syntax and which provides synchronous and predictable binding of code to each cell. A graphic work station is provided as a user interface to provide visual access to each cell or to cell groups for ease of control. The system can also function to emulate large scale integrated circuit processors by reason of the fine grain programmed operation of the system.
摘要翻译： 公开了一种特别用于解决实时推理问题的计算机系统。 该系统包括收缩细胞处理器，其提供可预测和响应的实时操作和细粒度可编程性。 该系统包括多个单独的处理器单元，每个单独的处理器单元具有其自己的本地存储器，该单元同时运行并且可操作以执行它们各自的程 全局存储器通过全局总线耦合到处理器单元，并向单元提供数据并存储来自单元的数据。 总线有效地同时访问所有单元到全局存储器。 该系统的另一个特征是使用英语语法的新颖的并行编程语言，并且提供了代码到每个单元的同步和可预测的绑定。 提供图形工作站作为用户界面，以提供对每个单元或单元组的可视访问以便于控制。 该系统还可以通过系统的细粒度编程操作来模拟大规模集成电路处理器。
-
10.发明授权
公开(公告)号：US4213174A
公开(公告)日：1980-07-15
申请号：US802261
申请日：1977-05-31
CPC分类号： G05B19/05 , G05B2219/11101 , G05B2219/1161 , G05B2219/14089 , G05B2219/14116 , G05B2219/14137 , G05B2219/15018 , G05B2219/15048 , G05B2219/15062 , G05B2219/15102
摘要： A programmable sequence controller is disclosed utilizing digital and analog inputs in order to generate digital output driver signals for the control of external systems or devices. The controller emulates mechanical sequence drums so that at any one time each of the simulated drums within the controller executes one of the addressable drum lines programmed within the drum. Each line of each simulated drum can be programmed to specify the energization or deenergization of any output driver as well as the energization or de-energization of any memory bit utilized by the controller in order to provide communication between drums. Each drum may also be programmed to have one or two sets of exit conditions, which if met, cause the controller to effectively rotate the drum to a specified drum line and execute this new drum line during the next scan of the controller. The controller can also sense emergency conditions and cause any or all of the drums to rotate to a specified line regardless of the drum line then being executed by the controller for each of the drums. An improved power-down, power-up circuitry insures an ordered and complete shutdown of the controller if any of a number of conditions exist, including utility AC failure and impending failure of several of the power supply voltages. Handshaking circuitry between the power supply and the remainder of the controller insures that the controller maintains memory validity for all types of shutdown situations, including momentary losses of any supply voltage.The programmable sequence controller includes a clock-calendar capable of continued operation during periods of extended power outages. The clock-calendar can be utilized in any drum line to form part of the control scheme.All programming of the simulated drum lines is performed through an interconnected data communication device such as a teletypewriter and utilizes a simple user-oriented language, with monitoring and diagnostic capability to facilitate debugging.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.027 秒)
