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公开(公告)号：US09202577B2
公开(公告)日：2015-12-01
申请号：US13976002
申请日：2012-06-07
CPC分类号： G11C16/16
摘要： Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了在功率损耗恢复中用于固态驱动器管理的设备，方法，计算机可读介质和系统配置。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09323542B2
公开(公告)日：2016-04-26
申请号：US13977081
申请日：2011-12-27
CPC分类号： G06F9/4403 , G06F3/0601 , G06F9/4401 , G06F12/10 , Y02D10/13
摘要： Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request.
摘要翻译： 各种实施例涉及用于更快的固态驱动（SSD）启动的装置和方法。 在启动时，SSD控制算法可以将非逻辑加载到上下文的物理（L2P）部分，并向系统通知SSD已准备就绪。 上下文可以包括与SSD相关的各种状态数据。 在指示SSD可能准备好接收访问请求之后，SSD控制算法可以开始依次加载L2P表的段。 但是，当请求的段尚未加载时，可能会阻止对L2P表的访问。 在这种情况下，SSD控制算法可以随后加载所请求的段，然后服务于访问请求。
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公开(公告)号：US09530461B2
公开(公告)日：2016-12-27
申请号：US13537553
申请日：2012-06-29
CPC分类号： G06F3/0625 , G06F1/3287 , G06F3/0655 , G06F3/0688 , G06F11/1417 , G11C5/148 , G11C7/1072 , G11C14/0009 , Y02D10/171
摘要： Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
摘要翻译： 利用包括一个或多个非易失性存储器件和易失性存储器系统的存储器子系统来利用非常低功率状态的技术。 存储器控制器与一个或多个非易失性存储器件和易失性存储器系统耦合。 存储器控制器至少包括嵌入式控制代理和存储状态信息的存储器位置。 存储器控制器，用于选择性地启用和禁用一个或多个非易失性存储器件。 存储器控制器在进入低功率状态之前将状态信息传送到易失性存储器系统。 控制电路与存储器控制器耦合。 所述控制电路用于选择性地启用和禁用所述存储器控制器的操作。
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公开(公告)号：US08244970B2
公开(公告)日：2012-08-14
申请号：US13074870
申请日：2011-03-29
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1417 , G06F11/1471 , G06F12/0802
摘要： An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
摘要翻译： 在执行操作系统高速缓存驱动器之前，设备以及系统，方法和文章可以操作以将写入操作的地址记录到由非易失性高速缓存的存储器中。 在一个实施例中，可以通过创建设备选项只读存储器（ROM）或修改相关联的计算机基本输入 - 输出系统（BIOS）来捕获与磁盘和其他媒体访问请求相关联的软件中断来实现非易失性高速缓存。 关联的地址，例如逻辑块地址，可以存储在修改的数据的日志中。 所得到的日志可以存储在非易失性介质中，包括缓存本身。 如果可用的日志空间不足以在加载操作系统驱动程序之前记录所有写入活动，则可以设置一个标志来指示超限状态。
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公开(公告)号：US07299379B2
公开(公告)日：2007-11-20
申请号：US10607772
申请日：2003-06-27
IPC分类号： G06F12/16
CPC分类号： G06F12/0804 , G06F11/1417 , G06F11/1471 , G06F12/0802
摘要： An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
摘要翻译： 在执行操作系统高速缓存驱动器之前，设备以及系统，方法和文章可以操作以将写入操作的地址记录到由非易失性高速缓存的存储器中。 在一个实施例中，可以通过创建设备选项只读存储器（ROM）或修改相关联的计算机基本输入 - 输出系统（BIOS）来捕获与磁盘和其他媒体访问请求相关联的软件中断来实现非易失性高速缓存。 关联的地址，例如逻辑块地址，可以存储在修改的数据的日志中。 所得到的日志可以存储在非易失性介质中，包括缓存本身。 如果可用的日志空间不足以在加载操作系统驱动程序之前记录所有写入活动，则可以设置一个标志来指示超限状态。
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公开(公告)号：US07937524B2
公开(公告)日：2011-05-03
申请号：US11856258
申请日：2007-09-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1417 , G06F11/1471 , G06F12/0802
摘要： An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
摘要翻译： 在执行操作系统高速缓存驱动器之前，设备以及系统，方法和文章可以操作以将写入操作的地址记录到由非易失性高速缓存的存储器中。 在一个实施例中，可以通过创建设备选项只读存储器（ROM）或修改相关联的计算机基本输入 - 输出系统（BIOS）来捕获与磁盘和其他媒体访问请求相关联的软件中断来实现非易失性高速缓存。 关联的地址，例如逻辑块地址，可以存储在修改的数据的日志中。 所得到的日志可以存储在非易失性介质中，包括缓存本身。 如果可用的日志空间不足以在加载操作系统驱动程序之前记录所有写入活动，则可以设置一个标志来指示超限状态。
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7.发明申请METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) 审中-公开元数据管理和支持相位变化记忆与开关（PCMS）公开(公告)号：US20140317337A1
公开(公告)日：2014-10-23
申请号：US13997215
申请日：2011-12-30
申请人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
发明人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
CPC分类号： G11C16/3431 , G06F11/1048 , G06F12/0246 , G11C13/0004 , G11C14/0045
摘要： Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与用于PCMS（带有交换机的相变存储器））元件的管理和/或支持相关的方法和装置。 在一个实施例中，PCMS控制器允许基于元数据访问PCMS设备。 可以使用元数据来提供如本公开中所讨论的效率，耐久性，纠错等。 还公开并要求保护其他实施例。
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8.发明授权Method and apparatus for efficient command queuing within a serial ATA environment 有权在串行ATA环境中有效的命令排队的方法和装置公开(公告)号：US06917992B2
公开(公告)日：2005-07-12
申请号：US10261755
申请日：2002-09-30
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0689
摘要： A method is described that involves sending a second command over a Serial ATA interface to a device before the device is able to execute a first command that was previously sent to the Serial ATA interface. In a further embodiment of the first command is tagged with a first reference number. In an even further embodiment of the method the second command is tagged with a second reference number.
摘要翻译： 描述了一种方法，其涉及在设备能够执行先前发送到串行ATA接口的第一命令之前，通过串行ATA接口向设备发送第二命令。 在第一命令的另一实施例中标记有第一参考号。 在该方法的又一实施例中，第二命令用第二参考号标记。
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9.发明授权Method and apparatus for generating a transportable physical level data block trace 有权用于生成可移动物理级数据块跟踪的方法和装置公开(公告)号：US06493806B1
公开(公告)日：2002-12-10
申请号：US09525199
申请日：2000-03-14
IPC分类号： G06F1200
CPC分类号： G06F11/3485
摘要： A system and method for generating a transportable physical level data block trace for a computer system. The method comprises capturing a first physical level data block trace on a first computer system, then performing a reverse file system lookup to generate a logical representation of that trace. That logical representation may be delivered to a second computer system, which may perform a file system lookup to convert the logical representation to a second physical level data block trace for a sequence of disk block accesses resulting from executing an application on the second computer system.
摘要翻译： 一种用于为计算机系统生成可移动物理级数据块跟踪的系统和方法。 该方法包括在第一计算机系统上捕获第一物理级数据块跟踪，然后执行反向文件系统查找以生成该跟踪的逻辑表示。 该逻辑表示可以被递送到第二计算机系统，该第二计算机系统可以执行文件系统查找以将逻辑表示转换为用于在第二计算机系统上执行应用程序导致的一系列磁盘块访问的第二物理级数据块跟踪。
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公开(公告)号：US20160034345A1
公开(公告)日：2016-02-04
申请号：US14775848
申请日：2014-02-26
CPC分类号： G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。
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