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公开(公告)号：US07986548B2
公开(公告)日：2011-07-26
申请号：US10536271
申请日：2003-10-29
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.
摘要翻译： 本发明提供一种用于通过在所选方向上重新路由选定位线的数字线电流来编程具有降低的电流消耗的磁随机存取存储器元件的方法和装置。
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2.发明授权MRAM-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference 有权MRAM单元和阵列架构，具有最大读出信号和降低的电磁干扰公开(公告)号：US07206220B2
公开(公告)日：2007-04-17
申请号：US10515475
申请日：2003-05-19
IPC分类号： G11C11/00
摘要： An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.
摘要翻译： 提出了一种提供最大读出信号的MRAM存储器。 这对于MRAM位的高速感测是有利的。 在具有连接在一起形成逻辑组织的行和列的磁阻存储器单元的MRAM存储器中，至少在写入期间通过将两个相邻行或列的写位线彼此连接来获得，以便将二进制数据值写入二 相邻的存储单元。 以这种方式，写入电流的返回路径以小环路提供，这增强了EMC行为。
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公开(公告)号：US07181655B2
公开(公告)日：2007-02-20
申请号：US10481570
申请日：2002-06-18
IPC分类号： G06F11/00
CPC分类号： G11C29/785 , G06F11/1016
摘要： The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
摘要翻译： 本发明涉及一种用于在其中使用冗余系统的存储装置中执行纠错的方法和电路装置。 通过应用相应的编码来冗余地记录故障单元的地址。 然后，在将故障地址信息与外部施加的地址进行比较之前，将错误校正应用于故障地址信息。 因此，可以防止由于冗余地址故障引起的错误。
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4.发明授权Magnetoresistive memory cell array and MRAM memory comprising such array 有权磁阻存储器单元阵列和包括这种阵列的MRAM存储器公开(公告)号：US07095648B2
公开(公告)日：2006-08-22
申请号：US10515155
申请日：2003-05-16
IPC分类号： G11C11/00
摘要： The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.
摘要翻译： 本发明描述了一种具有按逻辑组织的行和列布置的磁阻存储器单元的矩阵。每个存储单元包括磁阻元件。 矩阵包括用于同时从列中的一个单元读取并写入列中的另一个单元的装置，或用于同时从一行中的一个单元读取并写入同一行中的另一单元的装置。 这样的矩阵可以用在读写MRAM存储器中。
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公开(公告)号：US07663917B2
公开(公告)日：2010-02-16
申请号：US10560677
申请日：2004-06-10
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells (14) having a control gate connected to B and its source to A, and the other non-volatile element (16) having a control gate connected to A and its source to B. The drain of each non-volatile element (14, 16) is connected by means of a respective pMOS transistor (18, 20) to a program supply means.
摘要翻译： 一种静态存储单元，包括一对与非易失性存储元件（14,16）“遮蔽”的交叉耦合的反相器（10,12），使得写入静态存储器中的数据可以存储在非易失性单元 ，但也可以稍后回顾。 非易失性单元（14,16）被编程为相反的数据以增加检索过程的鲁棒性，并且它们与静态存储器单元的内部节点（A，B）交叉耦合，一个非易失性单元 具有与B连接的控制栅极的电池（14），其源极连接到A，而另一个非易失性元件（16）具有连接到A的控制栅极，其源极连接到B.每个非易失性元件（14）的漏极 ，16）通过相应的pMOS晶体管（18,20）连接到程序提供装置。
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公开(公告)号：US06980472B2
公开(公告)日：2005-12-27
申请号：US10498449
申请日：2002-12-05
IPC分类号： G11C16/06 , G11C5/00 , G11C16/02 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26
摘要： The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells.A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage.A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.
摘要翻译： 本发明涉及电子存储器，更具体地说，涉及一种读取紧凑型2-晶体管闪存单元的内容的改进方法和装置。 提供读取2晶体管闪存单元1的方法。 存储单元1包括具有存储栅极6的存储晶体管2和具有选择栅极7的选择晶体管3。 该方法包括在选择栅极7从第一电压切换到第二电压的同时使存储栅极6浮动，由此第一电压低于第二电压。 根据本发明的装置包括用于在选择栅极7从第一电压切换到第二电压时使存储栅极6离开的开关电路，第一电压低于第二电压。
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7.发明申请Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference 有权具有最大读出信号和降低电磁干扰的Mram-cell和阵列架构公开(公告)号：US20060056223A1
公开(公告)日：2006-03-16
申请号：US10515475
申请日：2003-05-19
申请人： Anthonie Ditewig , Roger Cuppens
发明人： Anthonie Ditewig , Roger Cuppens
IPC分类号： G11C11/22
摘要： An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.
摘要翻译： 提出了一种提供最大读出信号的MRAM存储器。 这对于MRAM位的高速感测是有利的。 在具有连接在一起形成逻辑组织的行和列的磁阻存储器单元的MRAM存储器中，至少在写入期间通过将两个相邻行或列的写位线彼此连接来获得，以便将二进制数据值写入二 相邻的存储单元。 以这种方式，写入电流的返回路径以小环路提供，这增强了EMC行为。
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8.发明授权Semiconductor device having an embedded non-volatile memory and method of manufacturing such a semicondutor device 失效具有嵌入式非易失性存储器的半导体器件和制造这种半导体器件的方法
公开(公告)号：US5879990A
公开(公告)日：1999-03-09
申请号：US814868
申请日：1997-03-11
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L29/42324
摘要： The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.
摘要翻译： 本发明特别涉及具有带有浮动栅极（10）的嵌入式非易失性存储器的集成电路（尽管并非排他地）。 根据本发明，对于该装置使用至少两个相等或至少基本相等厚度的多层。 第一多晶硅层poly是用于浮置栅极（10）和电路的逻辑部分中的NMOS和PMOS的栅极（22）。 第二多晶硅层poly B专门用于浮栅之上的控制电极（21）。 如果需要，可以为控制电极和逻辑门两者沉积第三多晶硅层，使得这些电极的厚度以及因此它们的电阻被赋予所需的值。 由于控制电极和逻辑门具有相同的厚度，所以防止了在浇注过程中过蚀刻和桥接的问题。
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9.发明授权Non-volatile, programmable semiconductor memory having reduced testing time 失效非易失性，可编程半导体存储器具有缩短的测试时间
公开(公告)号：US4862418A
公开(公告)日：1989-08-29
申请号：US266346
申请日：1988-11-01
CPC分类号： G11C29/24
摘要： In programmable memories of the EPROM or EEPROM type, a row and/or column of test memory cells are added to the matrix of rows and columns of non-volatile memory cells for the testing of the peripheral circuits which select and read the memory cells. The test memory cells have a very short write time as compared with the non-volatile memory cells and may be of the dynamic (or volatile) type. The write time for a memory cell of the EPROM or EEPROM may be, for example, 10 msec. The write time for a dynamic memory cell, however, is 100 nsec. The time required for testing the peripheral circuits can therefore be reduced by a factor of 80 (for a 16 Kbit memory) or higher (for memories larger than 16 Kbits).
摘要翻译： 在EPROM或EEPROM类型的可编程存储器中，测试存储器单元的行和/或列被添加到非易失性存储单元的行和列的矩阵中，用于测试选择和读取存储单元的外围电路。 测试存储单元与非易失性存储单元相比具有非常短的写入时间，并且可以是动态（或易失性）类型。 EPROM或EEPROM的存储单元的写入时间可以是例如10毫秒。 然而，动态存储单元的写入时间为100ns。 因此，测试外围电路所需的时间可以降低80倍（对于16 Kbit存储器）或更高（对于大于16 Kbits的存储器）。
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公开(公告)号：US4616339A
公开(公告)日：1986-10-07
申请号：US618006
申请日：1984-06-06
CPC分类号： G11C16/12
摘要： Field effect transistors having a short channel length are desirable for carrying out logic operations at a high speed. However, they are then not capable of withstanding the comparatively high programming and erasing voltage at which an (E)EPROM has to be operated. During the programming cycle the field effect transistors are kept in the current-nonconducting state, while recording the logic information obtained by the logic operations, the "fast" transistors are nevertheless capable of withstanding the comparatively high voltage.
摘要翻译： 具有短信道长度的场效应晶体管对于高速执行逻辑运算是理想的。 然而，它们不能承受必须操作（E）EPROM的相对较高的编程和擦除电压。 在编程周期期间，场效应晶体管保持在电流 - 非导通状态，同时记录通过逻辑运算获得的逻辑信息，但是“快速”晶体管仍能承受较高的电压。
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