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1.发明授权Electrical junction device with lightly doped buffer region to precisely locate a p-n junction 失效具有轻掺杂缓冲区域的电连接器件，以精确定位p-n结
公开(公告)号：US5404028A
公开(公告)日：1995-04-04
申请号：US7705
申请日：1993-01-22
IPC分类号： H01L29/205 , H01L21/331 , H01L29/15 , H01L29/73 , H01L29/737 , H01L29/161 , H01L29/72
CPC分类号： H01L29/155 , H01L29/7371
摘要： An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter. A p-n junction is formed within the superlattice, which functions on one side as an electrical extension of the emitter and on the other side as an electrical extension of the buffer, and establishes the electrical junction at the p-n junction location. The precise positioning of the electrical junction results in a known and repeatable emitter-base turn-on voltage.
摘要翻译： 通过在两种材料之间提供轻掺杂的p型缓冲区，掺杂水平在n掺杂材料的数量级上，电接点精确地位于高掺杂p型半导体材料和更轻掺杂的半导体材料之间。 尽管掺杂剂从p掺杂材料的扩散，缓冲区被制成足够宽以在大约与n掺杂材料的界面处建立电连接。 当应用于异质结双极晶体管（HBT）时，晶体管的基极用作重p掺杂材料，其发射极是较轻掺杂的材料。 缓冲区优选与位于缓冲区和发射极之间的渐变超晶格结合使用，其抑制掺杂剂从基极扩散到发射极中。 在超晶格内形成p-n结，其在一侧作为发射极的电延伸，另一侧作为缓冲器的电延伸而起作用，并在p-n结位置建立电连接。 电连接的精确定位导致已知且可重复的发射极基极导通电压。
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公开(公告)号：US5365077A
公开(公告)日：1994-11-15
申请号：US7695
申请日：1993-01-22
IPC分类号： H01L29/737 , H01L29/72 , H01L29/205
CPC分类号： H01L29/7371
摘要： A gain-stable npn heterojunction bipolar transistor includes a graded superlattice between its base and emitter consisting of multiple discrete periods, with each period having a layer of base material and another layer of emitter material. The thicknesses of the base material layers decrease while the thicknesses of the emitter material layers increase in discrete steps for each successive period from the base to the emitter. The thickness of each period is preferably at least about 20 Angstroms, with the superlattice including more than five periods. The superlattice is preferably doped to establish an electrical base-emitter junction at a desired location. The graded superlattice inhibits the diffusion of beryllium p dopant from the base into the emitter during transistor operation, thus stabilizing the device's gain and turn-on voltage.
摘要翻译： 增益稳定的npn异质结双极晶体管包括在其基极和发射极之间的由多个离散周期组成的分级超晶格，每个周期具有一层基底材料和另一层发射极材料。 基底层的厚度减小，而发射体材料层的厚度在从基底到发射体的每一个连续的周期内以离散的步长增加。 每个周期的厚度优选为至少约20埃，超晶格包括多于五个周期。 超晶格优选地被掺杂以在期望位置建立电基极 - 发射极结。 在晶体管操作期间，分级超晶格抑制铍p掺杂剂从基极扩散到发射极，从而稳定器件的增益和导通电压。
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公开(公告)号：US5532486A
公开(公告)日：1996-07-02
申请号：US387507
申请日：1995-02-13
IPC分类号： H01L29/205 , H01L29/861 , H01L31/0328
CPC分类号： H01L29/205 , H01L29/861 , Y10S257/916
摘要： A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate. A compositional grading can be provided at the heterojunction to reduce energy band spikes, and a region of low dopant concentration is included in the wider bandgap material to increase the diode's reverse-bias breakdown voltage.
摘要翻译： 具有低正向偏置导通电压的高速二极管通过具有窄度不大于约0.4eV的窄带隙能量的掺杂半导体材料层与具有不超过约0.4eV的相反掺杂半导体材料的层之间的异质结形成， 一个实质上更宽的带隙能量。 尽管在低带隙材料中可能产生应变和大量晶格位错的两种材料之间晶格不匹配，器件以比以前可获得的更低的导通电压工作。 选择两种材料使得异质结的价带和导带边缘不连续能够实现正向载流，但在正向偏置条件下阻塞跨接点的反向载流。 优选的材料系统是用于窄带隙材料的InAs，用于更宽带隙材料的InGaAs和用于衬底的InP，或用于更宽带隙材料的AlSb和用于衬底的GaSb。 可以在异质结处提供组成分级以减少能带尖峰，并且较宽带隙材料中包括低掺杂剂浓度的区域以增加二极管的反偏压击穿电压。
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4.发明授权Method for making fully self-aligned submicron heterojunction bipolar transistor 失效完全自对准亚微米异质结双极晶体管的方法
公开(公告)号：US5665614A
公开(公告)日：1997-09-09
申请号：US470811
申请日：1995-06-06
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S438/944
摘要： A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer. Emitter, base and collector contacts are simultaneously formed, the base contact aligned to the edge of the emitter cap overhang and the collector contact aligned to the edge of the base/collector layer overhang.
摘要翻译： 公开了一种亚微米发射极异质结双极晶体管及其制造方法。 制造工艺包括在半绝缘半导体衬底上依次顺序地对子集电极，集电极，基极，发射极和发射极盖层进行晶格匹配生长。 形成发射极盖台面，发射极/基极/集电极台面和子集电极台面。 形成介质平台，横向延伸基底/收集器层。 侧壁形成在发射极盖台面的侧面，并且延伸的基底/集电体层和底切部分的侧面被蚀刻到发射极层和子集电极层的上部。 这相对于发射极层在发射极盖台面上相对于子集电极层的上部形成在基极/集电极层上的突出端。 发射极，基极和集电极触点同时形成，基极触点与发射极帽突出端的边缘对准，并且集电极触点对准基极/集电极层突出端的边缘。
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5.发明授权Method for making integrated heterojunction bipolar/high electron mobility transistor 失效制造集成异质结双极/高电子迁移率晶体管的方法
公开(公告)号：US5920773A
公开(公告)日：1999-07-06
申请号：US876277
申请日：1997-06-16
IPC分类号： H01L21/285 , H01L21/331 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66318 , H01L21/28587 , H01L29/66462 , Y10S148/072
摘要： An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.
摘要翻译： 集成电路技术将异质结双极晶体管（HBT），高电子迁移率晶体管（HEMT）和其他部件以及互连金属化在一个基板上相结合。 在优选实施例中，使用干蚀刻对平坦基板进行图案化以在最终支持HEMT的位置提供一个或多个台面。 包括HEMT和HBT层的器件堆叠通过分子束外延在衬底上构建，活性HEMT器件位于HBT层中的开口内的台面上。 以这种方式，有源HEMT与HBT层对准，以使成品集成电路平坦化。
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6.发明授权Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors 失效异质结双极晶体管的基极 - 集电极结寄生电容的减小
公开(公告)号：US5468659A
公开(公告)日：1995-11-21
申请号：US209339
申请日：1994-03-10
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L29/205 , H01L29/737 , H01L21/265 , H01L21/20
CPC分类号： H01L29/66318 , H01L21/7605 , H01L29/7371 , Y10S438/951
摘要： A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.
摘要翻译： 使用与湿化学蚀刻和氧化硅蒸发和自对准剥离相结合的光刻胶工艺来减少基于InP的异质结双极晶体管（HBT）的寄生（非本征）基极 - 集电极结电容（CBC）。 与本底接触相关的台面的至少一部分蚀刻在固有器件区域周围，然后用蒸发的氧化物反向填充。 然后在背面填充的氧化物上形成基底接触垫，从而减少外部器件面积。 该方法在一个单一光致抗蚀剂加工步骤中提供台面的自对准蚀刻和后填充氧化物的沉积和剥离。 该方法简单可重现，提供非常高的产量。 它还消除了对昂贵且复杂的干蚀刻技术的需要。
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公开(公告)号：US5572049A
公开(公告)日：1996-11-05
申请号：US422110
申请日：1995-04-14
IPC分类号： H01L29/08 , H01L29/737 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7371 , H01L29/0821
摘要： A multi-layer collector heterojunction transistor (10) provides for high power, high efficiency transistor amplifier operation, especially in the RF (radio frequency) range of operation. A larger band gap first collector layer (12), approximately 15% of the active collector region (11) thickness, is provided at the base-collector junction (13). A smaller band gap second collector layer (14) forms the remainder of the active collector region (11). The multi-layer collector structure provides higher reverse bias breakdown voltage and higher carrier mobility during relevant portions of the output signal swing. A lower saturation voltage limit, or "knee" voltage, is provided at the operating points where linear operating regions transition to saturation operating regions as depicted in the output voltage-current (I-V) characteristic curves. The magnitude of the output signal swing of an amplifier may be increased, providing higher power amplification with greater power efficiency. The power supply voltage for the amplifier may be increased, providing for the use of a smaller, lighter power supply.
摘要翻译： 多层收集器异质结晶体管（10）提供高功率，高效率的晶体管放大器操作，特别是在RF（射频）操作范围内。 在基极 - 集电极结（13）处提供大约15％的有源集电极区域（11）厚度的较大的带隙第一集电极层（12）。 较小的带隙第二集电极层（14）形成有源集电极区域（11）的剩余部分。 多层收集器结构在输出信号摆幅的相关部分期间提供更高的反向偏压击穿电压和较高的载流子迁移率。 在输出电压 - 电流（I-V）特性曲线中描绘的线性工作区域转变到饱和工作区域的工作点处，提供较低的饱和电压限制或“拐点”电压。 可以增加放大器的输出信号摆幅的大小，以更高的功率效率提供更高的功率放大。 可以增加放大器的电源电压，从而提供更小，更轻的电源的使用。
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公开(公告)号：US5322808A
公开(公告)日：1994-06-21
申请号：US20095
申请日：1993-02-19
申请人： April S. Brown , Joseph A. Henige , Mark Lui , Loi Nguyen , Robert A. Metzger , William E. Stanchina
发明人： April S. Brown , Joseph A. Henige , Mark Lui , Loi Nguyen , Robert A. Metzger , William E. Stanchina
IPC分类号： H01L29/812 , H01L21/20 , H01L21/203 , H01L21/335 , H01L21/338 , H01L29/36 , H01L29/778 , H01L21/265
CPC分类号： H01L29/66462 , H01L21/02392 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/02584 , H01L21/02631 , H01L29/7781 , H01L29/7784 , H01L29/365 , Y10S148/072 , Y10S438/925
摘要： A donor layer (17) including an undoped wide bandgap material (14) and an n-type dopant (16) is deposited on a substrate (12) by molecular beam epitaxy (MBE) at a first temperature which is high enough for optimal growth of the donor layer (17). The dopant (16) is silicon or another material which exhibits surface segregation in the wide bandgap material (14) at the first temperature. An undoped spacer layer (18) of the wide bandgap material is deposited on the donor layer (17) at a second temperature which is sufficiently lower than the first temperature that surface segregation of the dopant material from the donor layer (17) into the spacer layer (18) is substantially suppressed. A channel layer (20) of a narrow bandgap material is formed on the spacer layer (18) at a third temperature which is higher than the second temperature and selected for optimal growth of the channel layer (20). The spacer layer (18) is substantially undoped, and the low temperature growth and reduction of donor movement reduces ionized impurity scattering in the channel layer (20).
摘要翻译： 包含未掺杂的宽带隙材料（14）和n型掺杂剂（16）的施主层（17）通过分子束外延（MBE）在第一温度下沉积在衬底（12）上，该第一温度足够高以达到最佳生长 的供体层（17）。 掺杂剂（16）是在第一温度下在宽带隙材料（14）中显示表面偏析的硅或另一种材料。 宽带隙材料的未掺杂的间隔层（18）在第二温度下沉积在施主层（17）上，第二温度足够低于掺杂剂材料从施主层（17）的表面偏析到间隔物 层（18）被基本抑制。 窄间隙材料的沟道层（20）在高于第二温度的第三温度下在间隔层（18）上形成，并被选择用于沟道层（20）的最佳生长。 间隔层（18）基本上未掺杂，并且供体运动的低温生长和还原降低了沟道层（20）中的电离杂质散射。
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9.发明授权NPN heterojunction bipolar transistor including antimonide base formed on semi-insulating indium phosphide substrate 失效NPN异质结双极晶体管，包括在半绝缘磷化铟衬底上形成的锑化物基底
公开(公告)号：US5349201A
公开(公告)日：1994-09-20
申请号：US889864
申请日：1992-05-28
IPC分类号： H01L21/331 , H01L29/15 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/161 , H01L27/12
CPC分类号： H01L29/7371 , H01L29/155 , H01L29/205
摘要： A heterojunction bipolar transistor (HBT) (10,30) includes an indium-gallium-arsenide (InGaAs), indium-phosphide (InP) or aluminum-indium-arsenide (AlInAs) collector layer (14) formed over an indium-phosphide (InP) substrate (12). A base layer (16,32) including gallium (Ga), arsenic (As) and antimony (Sb) is formed over the collector layer (14), and an AlInAs or InP emitter layer (18) is formed over the base layer (16,32). The base layer may be ternary gallium-arsenide-antimonide (GaAsSb) doped with beryllium (Be) (16), or a strained-layer-superlattice (SLS) structure (32) including alternating superlattice (32b,32a) layers of undoped gallium-arsenide (GaAs) and P-doped gallium-antimonide (GaSb). The GaSb superlattice layers (32a) are preferably doped with silicon (Si), which is much less diffusive than Be.
摘要翻译： 异质结双极晶体管（HBT）（10,30）包括形成在铟磷化物上的铟 - 砷化镓（InGaAs），铟 - 磷化物（InP）或铝 - 砷化铟（AlInAs）集电极层（14） InP）衬底（12）。 在集电极层（14）上形成包括镓（Ga），砷（As）和锑（Sb）的基底层（16,32），并且在基底层上形成AlInAs或InP发射极层（18） 16,32）。 基底层可以是掺杂有铍（Be）（16）的三元砷化镓 - 锑化物（GaAsSb）或包括未掺杂镓的交替超晶格（32b，32a）层的应变层超晶格（SLS）结构（32） 砷化镓（GaAs）和P掺杂的锑化镓（GaSb）。 GaSb超晶格层（32a）优选掺杂有硅（Si），其比Be更少扩散。
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公开(公告)号：US5889487A
公开(公告)日：1999-03-30
申请号：US841833
申请日：1997-05-05
CPC分类号： B82Y10/00 , H03K19/212 , H03K3/315 , H03M1/365
摘要： The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.
摘要翻译： 通过将输入锁存功能合并到转换器解码部分中使用的异或门，闪存模数转换器中的输入锁存比较器的数量显着减少。 用于此目的的锁存异或门将谐振隧道二极管用作锁存装置，其中连接有滞后和阻抗元件，以确保栅极锁存在对应于输入模拟信号的逻辑状态。 锁存逻辑门以当前模式工作，使更新的逻辑状态能够响应于周期性时钟信号被锁存。
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