公开(公告)号：US20050191808A1

公开(公告)日：2005-09-01

申请号：US10787510

申请日：2004-02-26

申请人： Robert Steimle ,  Jane Yater ,  Gowrishankar Chindalore ,  Craig Swift ,  Steven Anderson ,  Ramachandran Muralidhar

发明人： Robert Steimle ,  Jane Yater ,  Gowrishankar Chindalore ,  Craig Swift ,  Steven Anderson ,  Ramachandran Muralidhar

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/44 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/792

CPC分类号： H01L21/32135 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32134 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526

摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

摘要翻译： 纳米簇被覆盖在集成电路上，然后从不需要纳米团簇的区域去除。 在毛毯沉积之前在纳米团簇不需要的那些区域中形成牺牲层。 然后去除纳米团簇和牺牲层。 在一种形式中，牺牲层包括沉积的含氮化物或含氧化物层。 或者，牺牲层包括先前用于在衬底中形成隔离区域的衬垫氧化物或衬垫氮化物层中的至少一个。 然后可以将纳米簇装置和非纳群集装置集成到相同的集成电路上。 牺牲层的使用保护下层，从而防止随后形成的非纳群集装置的性能下降。

公开(公告)号：US07642163B2

公开(公告)日：2010-01-05

申请号：US11693829

申请日：2007-03-30

申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

摘要翻译： 电子设备可以包括在电介质层内具有DSE的非易失性存储单元。 一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。 该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。 在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。 在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。 在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

公开(公告)号：US20080242022A1

公开(公告)日：2008-10-02

申请号：US11693829

申请日：2007-03-30

申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

摘要翻译： 电子设备可以包括在电介质层内具有DSE的非易失性存储单元。 一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。 该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。 在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。 在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。 在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

公开(公告)号：US20060194438A1

公开(公告)日：2006-08-31

申请号：US10876820

申请日：2004-06-25

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

IPC分类号： H01L21/302 ,  H01L31/112 ,  H01L21/36

CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42332

摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.

摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

公开(公告)号：US20060046406A1

公开(公告)日：2006-03-02

申请号：US10930892

申请日：2004-08-31

申请人： Gowrishankar Chindalore ,  James Burnett ,  Craig Swift ,  Ramachandran Muralidhar

发明人： Gowrishankar Chindalore ,  James Burnett ,  Craig Swift ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66833 ,  H01L29/7881

摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.

摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

公开(公告)号：US20060043482A1

公开(公告)日：2006-03-02

申请号：US10930891

申请日：2004-08-31

申请人： James Burnett ,  Gowrishankar Chindalore ,  Craig Swift ,  Ramachandran Muralidhar

发明人： James Burnett ,  Gowrishankar Chindalore ,  Craig Swift ,  Ramachandran Muralidhar

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/7881 ,  H01L29/7885

摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.

公开(公告)号：US20070019472A1

公开(公告)日：2007-01-25

申请号：US11188898

申请日：2005-07-25

申请人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

发明人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

公开(公告)号：US20050041503A1

公开(公告)日：2005-02-24

申请号：US10950855

申请日：2004-09-27

申请人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

发明人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

IPC分类号： G11C5/00 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.

摘要翻译： 非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。 存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。 在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。 除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。 通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移 ，51,53）。 提供读控制电路（42）以偏置参考晶体管（46）的栅极。 读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

公开(公告)号：US20050161731A1

公开(公告)日：2005-07-28

申请号：US10765804

申请日：2004-01-27

申请人： Paul Ingersoll ,  Gowrishankar Chindalore ,  Ramachandran Muralidhar

发明人： Paul Ingersoll ,  Gowrishankar Chindalore ,  Ramachandran Muralidhar

IPC分类号： C09K17/14 ,  C09K17/40 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/16 ,  H01L29/423 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮置栅极16上。在一个实施例中，分立元件22预先形成为气相并且附着到半导体 装置10通过静电力。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。

公开(公告)号：US20080019178A1

公开(公告)日：2008-01-24

申请号：US11834391

申请日：2007-08-06

申请人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

发明人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/10

摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。