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    Circuit manufacturing and design techniques for reference plane voids with strip segment
    2.
    发明授权
    Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
    具有带段的参考平面空隙的电路制造和设计技术

    公开(公告)号：US08325490B2

    公开(公告)日：2012-12-04

    申请号：US12823316

    申请日：2010-06-25

    Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC: H05K1/11

    CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Structure for enhancing reference return current conduction
    3.
    发明授权
    Structure for enhancing reference return current conduction 失效
    用于增强参考回流导通的结构

    公开(公告)号：US08295058B2

    公开(公告)日：2012-10-23

    申请号：US12641381

    申请日：2009-12-18

    Applicant: Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

    Inventor： Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

    IPC: H05K1/11 ,  H05K7/14 ,  H05K9/00

    CPC classification number: H05K1/0251 ,  G06F17/5077 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09536

    Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

    Abstract translation: 提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

    System DC Analysis Methodology
    6.
    发明授权
    System DC Analysis Methodology 有权
    系统直流分析方法

    公开(公告)号：US07460986B2

    公开(公告)日：2008-12-02

    申请号：US11380058

    申请日：2006-04-25

    Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    IPC: G06F17/50 ,  G06F19/00

    CPC classification number: G06F17/5036

    Abstract: A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.

    Abstract translation: 提供了一种用于分层系统的功率传递分析和设计的方法。 该方法包括建立与分级系统的每个元素相对应的模型，编译包含对应于分层系统的每个元素的模型的存储库，其中存储库包括网络列表，域列表，组件列表，引脚列表 ，和一个图层列表。 该方法还包括对分层系统的每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化，以及从存储库中包含的模型组装系统模型。 此外，该方法包括通过将系统模型转换为完全由电阻组成的扁平化系统模型，并在扁平化系统模型上运行模拟来平坦化系统模型。

    Power delivery analysis and design
    10.
    发明授权
    Power delivery analysis and design 有权
    电力分配和设计

    公开(公告)号：US08055486B2

    公开(公告)日：2011-11-08

    申请号：US12187164

    申请日：2008-08-06

    Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.

    Abstract translation: 提供计算机程序产品用于分层系统的功率传递分析和设计。 该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。 该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层 列表。 该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

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