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    Circuit manufacturing and design techniques for reference plane voids with strip segment
    7.
    发明授权
    Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
    具有带段的参考平面空隙的电路制造和设计技术

    公开(公告)号：US08325490B2

    公开(公告)日：2012-12-04

    申请号：US12823316

    申请日：2010-06-25

    Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC: H05K1/11

    CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Structure for enhancing reference return current conduction
    8.
    发明授权
    Structure for enhancing reference return current conduction 失效
    用于增强参考回流导通的结构

    公开(公告)号：US08295058B2

    公开(公告)日：2012-10-23

    申请号：US12641381

    申请日：2009-12-18

    Applicant: Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

    Inventor： Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

    IPC: H05K1/11 ,  H05K7/14 ,  H05K9/00

    CPC classification number: H05K1/0251 ,  G06F17/5077 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09536

    Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

    Abstract translation: 提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

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