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    Timing calibration and timing calibration verification of electronic circuit testers
    2.
    发明授权
    Timing calibration and timing calibration verification of electronic circuit testers 失效
    电子测试仪的定时校准和定时校准验证

    公开(公告)号：US06570397B2

    公开(公告)日：2003-05-27

    申请号：US09923548

    申请日：2001-08-07

    申请人： Romi Mayder ,  Noriyuki Sugihara ,  Andrew Tse ,  Randy L. Bailey

    发明人： Romi Mayder ,  Noriyuki Sugihara ,  Andrew Tse ,  Randy L. Bailey

    IPC分类号： G01R3102

    CPC分类号： G01R31/319 ,  G01R31/3191 ,  G01R31/3193 ,  G01R31/31937 ,  G01R35/00 ,  G01R35/005

    摘要： Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time. In some embodiments, test channels are connected directly to calibration board comparators to avoid the accumulated signal degradation and the signal path route errors that may result from transmitting tester channel signals through a mechanical relay selection matrix.

    摘要翻译： 描述了用于校准电子电路测试器的定时和验证电子电路测试器的定时校准的系统和方法。 在一些实施例中，校准参考信号从测试头直接通过负载板接口而不是通过外部仪器传输，从而可以避免与外部电线和电缆相关联的定时误差。 在单个校准板上提供定时校准和定时校准验证功能，从而相对于传统的基于机器人的校准器减少校准设置时间。 此外，高引脚数电子电路测试器可以由校准板校准，校准板被配置为一次校准测试通道的一个子集。 在一些实施例中，测试通道直接连接到校准板比较器，以避免由于通过机械继电器选择矩阵发送测试仪通道信号而导致的累积信号劣化和信号路径路由错误。

    Parallel calibration system for a test device
    3.
    发明申请
    Parallel calibration system for a test device 有权
    用于测试设备的并行校准系统

    公开(公告)号：US20060006896A1

    公开(公告)日：2006-01-12

    申请号：US10886848

    申请日：2004-07-08

    申请人： Romi Mayder ,  Todd Sholl ,  Nasser Jafari ,  Andrew Tse ,  Randy Bailey

    发明人： Romi Mayder ,  Todd Sholl ,  Nasser Jafari ,  Andrew Tse ,  Randy Bailey

    IPC分类号： G01R31/02

    CPC分类号： G01R31/3191 ,  G01R35/005

    摘要： A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

    摘要翻译： 用于电子电路测试器的并行校准系统包括测试和测量电子器件，耦合到测试和测量电子器件的测试夹具，测试夹具包括时钟参考电路和时钟分配电路，被测器件接口以及多个校准板 耦合到被测设备的接口，其中所述多个校准板和所述时钟分配电路同时测试多个测试通道的信号路径。

    Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array
    5.
    发明申请
    Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array 有权
    用于在测试仪与被测试的多个器件之间处理信号的装置，系统和方法在高温下并且具有探针阵列的单次触地

    公开(公告)号：US20070247140A1

    公开(公告)日：2007-10-25

    申请号：US11410699

    申请日：2006-04-24

    申请人： Romi Mayder ,  Pam Stellmacher ,  Edmundo Puente ,  John Andberg

    发明人： Romi Mayder ,  Pam Stellmacher ,  Edmundo Puente ,  John Andberg

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2889

    摘要： Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. A method of processing signals between a tester and devices under test is disclosed. In an embodiment, the method includes connecting the tester and the devices under test with at least one multichip module. Each of the at least one multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to the devices under test. The method includes operating each of the micro-electromechanical switches. Other embodiments are also disclosed.

    摘要翻译： 设备用于在测试仪和被测设备之间处理信号。 在一个实施例中，该装置包括至少一个多芯片模块。 每个多芯片模块在一组连接器与测试器之间具有多个微机电开关，以及一组连接器到被测器件。 提供至少一个驱动器以操作每个微机电开关。 公开了一种在测试仪和被测器件之间处理信号的方法。 在一个实施例中，该方法包括用至少一个多芯片模块连接测试器和被测设备。 所述至少一个多芯片模块中的每一个具有在到所述测试器的一组连接器之间的多个微机电开关和一组到所述被测器件的连接器。 该方法包括操作每个微机电开关。 还公开了其他实施例。

    Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment
    7.
    发明授权
    Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment 有权
    模拟晶圆，使用模拟晶圆校准的系统以及校准自动测试设备的方法

    公开(公告)号：US07323897B2

    公开(公告)日：2008-01-29

    申请号：US11014473

    申请日：2004-12-16

    申请人： Romi Mayder

    发明人： Romi Mayder

    IPC分类号： G01R31/26

    CPC分类号： G01R35/005 ,  G01R31/2886

    摘要： In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for calibrating automated test equipment (ATE) may include coupling the mock wafer to the ATE, and then causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes or the test head connector to a number of the mock wafer's mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

    摘要翻译： 在一个实施例中，用于校准自动测试设备的模拟晶片包括具有多个互连区域的印刷电路板，每个互连区域具有通过连接迹线耦合的一对模拟管芯焊盘。 在另一个实施例中，用于校准自动化测试设备（ATE）的方法可以包括将模拟晶片耦合到ATE，然后使ATE相对于测试头连接器对模拟晶片进行索引，ii）将多个 探针或测试头连接器连接到多个模拟晶片的模拟芯片焊盘，iii）在通过一对模拟裸片焊盘和模拟晶片的连接迹线耦合的一对探针之间传输测试信号，以及iv） 通过记录发送的测试信号的特性来校准所选择的信号路径或ATE的路径。

    Zero insertion force printed circuit assembly connector system and method
    8.
    发明授权
    Zero insertion force printed circuit assembly connector system and method 有权
    零插入力印刷电路组件连接器系统和方法

    公开(公告)号：US07147499B1

    公开(公告)日：2006-12-12

    申请号：US11253446

    申请日：2005-10-19

    申请人： Romi Mayder ,  John W. Andberg ,  Don Chiu ,  Noriyuki Sugihara

    发明人： Romi Mayder ,  John W. Andberg ,  Don Chiu ,  Noriyuki Sugihara

    IPC分类号： H01R13/62

    CPC分类号： G01R31/2889

    摘要： In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.

    摘要翻译： 在一个实施例中，匹配电路组件通过1）将安装在第一和第二衬底中的至少一个上的至少第一插入件机械地和电耦合到配合电路组件而耦合到系统。 使用至少第一和第二弹簧机构实现机械和电耦合，其中第一和第二弹簧机构安装在连接器壳体与第一和第二基板中的相应的基板之间。 第一和第二基板中的至少一个在第一插入器和系统之间传输信号。 第一插入器通过在连接器壳体与第一和第二基板中的至少一个之间产生真空而与配合电路组件电气和机械地分离。 还公开了其他实施例。

    Dynamic configuration of equivalent series resistance
    9.
    发明授权
    Dynamic configuration of equivalent series resistance 有权
    等效串联电阻的动态配置

    公开(公告)号：US09377802B1

    公开(公告)日：2016-06-28

    申请号：US13414387

    申请日：2012-03-07

    申请人： Christopher P. Wyland ,  Romi Mayder ,  Paul Y. Wu

    发明人： Christopher P. Wyland ,  Romi Mayder ,  Paul Y. Wu

    IPC分类号： G05F1/652 ,  G05F1/63 ,  G05F1/44 ,  G05F1/12

    CPC分类号： G05F1/652 ,  G05F1/12 ,  G05F1/44 ,  G05F1/63

    摘要： In one embodiment, an integrated circuit (IC) includes a power distribution network having a first set of power distribution lines connected to a source voltage and a second set of power distribution lines connected to a ground voltage, and a first capacitor. A first variable resistive element is electrically coupled in series with the first capacitor between the first and second sets of power lines of the power distribution network. A control circuit is coupled to the variable resistive element and is configured and arranged to adjust a level of resistance of the first variable resistive element in response to an input signal. The adjustment of the level of resistance adjusts an equivalent series resistance of the power distribution network.

    摘要翻译： 在一个实施例中，集成电路（IC）包括配电网络，该配电网络具有连接到源极电压的第一组配电线路和连接到接地电压的第二组配电线路以及第一电容器。 第一可变电阻元件与配电网络的第一和第二组电力线之间的第一电容器串联电耦合。 控制电路耦合到可变电阻元件，并且被配置和布置成响应于输入信号调整第一可变电阻元件的电阻电平。 电阻水平的调整调整配电网的等效串联电阻。

    Method and apparatus for a paddle board probe card
    10.
    发明授权
    Method and apparatus for a paddle board probe card 有权
    桨板探针卡的方法和装置

    公开(公告)号：US07459921B2

    公开(公告)日：2008-12-02

    申请号：US11444645

    申请日：2006-05-31

    申请人： Romi Mayder ,  John W. Andberg

    发明人： Romi Mayder ,  John W. Andberg

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2889

    摘要： A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.

    摘要翻译： 提出了一种用于通过ZIF连接器将待测器件与ATE测试仪连接的桨板探针卡。 桨板探针卡可以包括安装在探针卡上的多于一个印刷电路板，使得多于一个印刷电路板与ATE测试头接口上的ZIF连接器配合。