公开(公告)号：US20110254075A1

公开(公告)日：2011-10-20

申请号：US13168902

申请日：2011-06-24

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L29/788 ,  B82Y99/00

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 闪存集成电路及其制造方法。 栅极堆叠包括直接与硅层接触的初始氧化物层，在其间界定氧化物 - 硅界面。 另外的氧化物材料沿着氧化硅 - 硅界面基本均匀地形成。 因此在界面处的多晶硅晶界被蚀刻后钝化。 界面可以形成在隧道氧化物和浮动栅极之间，钝化晶界可以减少擦除变化。 在稀释蒸汽氧化中，上储存电介质层中的氧化物增强。 薄氧化物层用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US07585725B2

公开(公告)日：2009-09-08

申请号：US12204603

申请日：2008-09-04

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide -nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

公开(公告)号：US08294192B2

公开(公告)日：2012-10-23

申请号：US13168902

申请日：2011-06-24

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 闪存集成电路及其制造方法。 栅极堆叠包括直接与硅层接触的初始氧化物层，在其间界定氧化物 - 硅界面。 另外的氧化物材料沿着氧化硅 - 硅界面基本均匀地形成。 因此在界面处的多晶硅晶界被蚀刻后钝化。 界面可以形成在隧道氧化物和浮动栅极之间，钝化晶界可以减少擦除变化。 在稀释蒸汽氧化中，上储存电介质层中的氧化物得到增强。 薄氧化物层用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US20090004794A1

公开(公告)日：2009-01-01

申请号：US12204603

申请日：2008-09-04

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US06949789B2

公开(公告)日：2005-09-27

申请号：US10013322

申请日：2001-11-13

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US06348380B1

公开(公告)日：2002-02-19

申请号：US09648699

申请日：2000-08-25

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21336

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

公开(公告)号：US20100032746A1

公开(公告)日：2010-02-11

申请号：US12534054

申请日：2009-07-31

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L29/788

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US07432546B2

公开(公告)日：2008-10-07

申请号：US11205772

申请日：2005-08-17

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L29/02

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US07084448B2

公开(公告)日：2006-08-01

申请号：US10786348

申请日：2004-02-24

申请人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

发明人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

摘要： A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

摘要翻译： 在形成半导体器件期间使用的方法包括提供晶片衬底组件，其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫，并且衬套设置在开口中。 形成数字线插头的一部分，然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触，然后使用衬垫和底板作为蚀刻停止层，第三次蚀刻电介质层。 形成电容器单元电介质层和电容器顶板，其提供双面容器单元。 形成附加的电介质层，然后蚀刻附加的电介质层，电池顶板和电池电介质以露出数字线插头部分。 最后，形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。

公开(公告)号：US06462371B1

公开(公告)日：2002-10-08

申请号：US09229320

申请日：1999-01-13

申请人： Ronald A. Weimer ,  John T. Moore

发明人： Ronald A. Weimer ,  John T. Moore

IPC分类号： H01L27108

CPC分类号： H01L21/0276 ,  H01L21/02126 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3145 ,  H01L21/3146 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S257/90 ,  Y10S438/97

摘要： The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

摘要翻译： 本发明涉及掺杂有碳的硅和氧的膜以及集成电路技术中的膜的使用，例如电容器结构，DRAM构造，半导体材料组件，蚀刻工艺以及用于形成电容器，DRAM和半导体的方法 材料组件