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    Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns
    7.
    发明授权
    Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns 有权
    一种具有存储阵列的存储器件的制造方法，所述存储器阵列包括以行和列排列的多个存储单元晶体管

    公开(公告)号：US08389357B2

    公开(公告)日：2013-03-05

    申请号：US13052728

    申请日：2011-03-21

    申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    IPC分类号： H01L21/336

    CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

    摘要： A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

    摘要翻译： 一种在半导体衬底中制造存储器件的方法，该器件具有存储器阵列，该存储器阵列具有排列成行和列的多个存储单元晶体管。 该方法包括形成多个隧穿场效应晶体管，形成第二掺杂类型的第一阱，形成围绕第一阱的第一掺杂类型的第二阱，形成连接到第一行存储单元晶体管的第一字线 形成第一位线，以控制第一列存储单元晶体管的隧穿场效应晶体管的掺杂漏极区的电压，以及形成与第一位线平行的第二位线。

    Integrated memory device having columns having multiple bit lines
    9.
    发明授权
    Integrated memory device having columns having multiple bit lines 有权
    具有多列位线的集成存储器件

    公开(公告)号：US08288813B2

    公开(公告)日：2012-10-16

    申请号：US10918335

    申请日：2004-08-13

    申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

    摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

    摘要翻译： 提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。 存储器件包括包含存储单元的行和列的矩阵。 每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。 存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。 第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

    INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES
    10.
    发明申请
    INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES 有权
    具有多个位线的列的集成存储器件

    公开(公告)号：US20110171803A1

    公开(公告)日：2011-07-14

    申请号：US13052728

    申请日：2011-03-21

    申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    IPC分类号： H01L21/336

    CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

    摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

    摘要翻译： 提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。 存储器件包括包含存储单元的行和列的矩阵。 每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。 存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。 第一掺杂区域具有与第二掺杂区域不同的掺杂类型。