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    Low skew differential receiver with disable feature
    2.
    发明授权
    Low skew differential receiver with disable feature 有权
    低偏差差分接收器具有禁用功能

    公开(公告)号：US6026051A

    公开(公告)日：2000-02-15

    申请号：US275690

    申请日：1999-03-24

    申请人： Brent Keeth ,  Russel J. Baker

    发明人： Brent Keeth ,  Russel J. Baker

    IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/018528 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  H03K19/00384

    摘要： A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock recciver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

    摘要翻译： 用于SynchLink型同步动态随机存取存储器（SLDRAM）的差分时钟接收器包括具有用于偏置其NMOS和PMOS电流源的新颖方法的差分放大器。 由差分放大器接收和放大的差分时钟切换一组多路复用器，其通过输出差分输出时钟来响应。 多路复用器可以通过无效使能信号“禁用”，因此它们为差分输出时钟输出一个恒定的“0”电平。 对于SLDRAM中发现的间歇性数据时钟，差分时钟接收器的禁用功能特别有用。 此外，差分放大器的电流源的新型偏置方法给时钟接收器非常低的偏移。

    Low skew differential receiver with disable feature
    3.
    发明授权
    Low skew differential receiver with disable feature 有权
    低偏差差分接收器具有禁用功能

    公开(公告)号：US6104209A

    公开(公告)日：2000-08-15

    申请号：US140857

    申请日：1998-08-27

    申请人： Brent Keeth ,  Russel J. Baker

    发明人： Brent Keeth ,  Russel J. Baker

    IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/018528 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  H03K19/00384

    摘要： A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

    摘要翻译： 用于SynchLink型同步动态随机存取存储器（SLDRAM）的差分时钟接收器包括具有用于偏置其NMOS和PMOS电流源的新颖方法的差分放大器。 由差分放大器接收和放大的差分时钟切换一组多路复用器，其通过输出差分输出时钟来响应。 多路复用器可以通过无效使能信号“禁用”，因此它们为差分输出时钟输出一个恒定的“0”电平。 差分时钟接收器的禁用功能对于SLDRAM中发现的间歇数据时钟特别有用。 此外，差分放大器的电流源的新型偏置方法给时钟接收器非常低的偏移。

    Low skew differential receiver with disable feature
    6.
    发明授权
    Low skew differential receiver with disable feature 有权
    低偏差差分接收器具有禁用功能

    公开(公告)号：US06256234B1

    公开(公告)日：2001-07-03

    申请号：US09577109

    申请日：2000-05-23

    申请人： Brent Keeth ,  Russel J. Baker

    发明人： Brent Keeth ,  Russel J. Baker

    IPC分类号： G11C700

    CPC分类号： H03K19/018528 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  H03K19/00384

    摘要： A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be “disabled” by an inactive enable signal so they output a constant “0” level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

    摘要翻译： 用于SynchLink型同步动态随机存取存储器（SLDRAM）的差分时钟接收器包括具有用于偏置其NMOS和PMOS电流源的新颖方法的差分放大器。 由差分放大器接收和放大的差分时钟切换一组多路复用器，其通过输出差分输出时钟来响应。 多路复用器可以通过无效使能信号“禁用”，因此它们为差分输出时钟输出一个恒定的“0”电平。 差分时钟接收器的禁用功能对于SLDRAM中发现的间歇数据时钟特别有用。 此外，差分放大器的电流源的新型偏置方法给时钟接收器非常低的偏移。

    WAFER-SCALE MEMORY TECHNIQUES
    7.
    发明申请
    WAFER-SCALE MEMORY TECHNIQUES 有权

    公开(公告)号：US20210240344A1

    公开(公告)日：2021-08-05

    申请号：US17162796

    申请日：2021-01-29

    申请人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    发明人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    IPC分类号： G06F3/06

    摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

    MEMORY DEVICE INTERFACE AND METHOD
    8.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 有权

    公开(公告)号：US20210200464A1

    公开(公告)日：2021-07-01

    申请号：US17136728

    申请日：2020-12-29

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G06F3/06

    摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    10.
    发明申请
    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
    基于命令信号和操作状态解码命令的系统和方法

    公开(公告)号：US20120246434A1

    公开(公告)日：2012-09-27

    申请号：US13489246

    申请日：2012-06-05

    申请人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F12/00

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。