公开(公告)号：US20100244186A1

公开(公告)日：2010-09-30

申请号：US12722920

申请日：2010-03-12

申请人： Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

发明人： Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

IPC分类号： H01L27/10 ,  H01L21/822 ,  G11C17/16

CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括沿第一方向堆叠的多个堆叠的元件单元，每个堆叠元件单元包括由垂直于第一元件垂直设置的第一导电类型的半导体制成的第一导电膜 方向和与第一导电膜在第一方向上堆叠的第一绝缘膜; 所述半导体柱在所述第一方向上穿透所述层叠结构单元，并且包括第二导电类型的导电区域，所述半导体柱包括与所述第一导电膜相对的第一区域，以及设置在所述第一区域之间的第二区域， 所述第一方向，所述第二区域具有与所述第一区域的电阻不同的电阻; 以及设置在所述半导体柱和所述第一导电膜之间的第二绝缘膜。

公开(公告)号：US20100320526A1

公开(公告)日：2010-12-23

申请号：US12727730

申请日：2010-03-19

申请人： Masaru KIDOH ,  Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI

发明人： Masaru KIDOH ,  Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L23/522 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 记忆单元 以及设置在半导体衬底和存储器单元之间的电路单元。 存储单元包括：层叠结构单元，其具有交替层叠有电极间绝缘膜的电极膜; 穿过堆叠结构单元的半导体柱; 以及与电极膜和半导体柱之间的交点对应地设置的存储单元。 电路单元包括具有不同导电类型的第一和第二晶体管，第一互连以及第一和第二接触插塞。 第一互连包括设置在与半导体衬底相对的第一和第二晶体管一侧的硅化物。 由第一导电类型的多晶硅制成的第一接触插头将第一互连件连接到第一晶体管。 由第二导电类型的多晶硅制成的第二接触插头将第一互连件连接到第二晶体管。

公开(公告)号：US20100207194A1

公开(公告)日：2010-08-19

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

发明人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

公开(公告)号：US20110298033A1

公开(公告)日：2011-12-08

申请号：US13051355

申请日：2011-03-18

申请人： Junya MATSUNAMI ,  Mitsuhiro NOGUCHI

发明人： Junya MATSUNAMI ,  Mitsuhiro NOGUCHI

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11524 ,  H01L29/7883

摘要： According to one embodiment, a semiconductor storage device includes a charge storage layer, a control gate. The charge storage layer is formed above a semiconductor substrate with first insulating film disposed therebetween. The control gate is formed above the charge storage layer with second insulating film disposed therebetween. The control gate includes a nickel silicide region. The side surface expands outwardly in at least a partial region thereof, and height of the control gate from a portion at which the side surface thereof starts to expand outwardly to a top of the control gate is greater than maximum width of the control gate in a region above the portion at which the side surface starts to expand outwardly.

摘要翻译： 根据一个实施例，半导体存储装置包括电荷存储层，控制栅极。 电荷存储层形成在半导体衬底之上，第一绝缘膜位于它们之间。 控制栅极形成在电荷存储层上方，其间设置有第二绝缘膜。 控制栅极包括硅化镍区域。 侧表面在其至少部分区域中向外扩张，并且控制门从其侧表面开始向外膨胀到控制栅极顶部的部分的高度大于控制栅极的最大宽度 在侧面开始向外膨胀的部分之上的区域。

公开(公告)号：US20130088910A1

公开(公告)日：2013-04-11

申请号：US13424499

申请日：2012-03-20

申请人： Junya MATSUNAMI

发明人： Junya MATSUNAMI

IPC分类号： G11C11/21

CPC分类号： G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0016 ,  G11C13/0026 ,  G11C13/0038 ,  G11C2013/0083

摘要： A non-volatile semiconductor memory device according to an embodiment includes a memory cell array including first lines, second lines, and memory cells each including a variable resistor and each connected between one of the first lines and one of the second lines, and a control circuit configured to perform a voltage application operation of applying a first voltage to a selected first line connected to a selected memory cell and applying a second voltage having a voltage value lower than the first voltage to a selected second line connected to the selected memory cell. The control circuit is configured to select the voltage value of the second voltage from among a plurality of different voltage values and output the second voltage.

摘要翻译： 根据实施例的非易失性半导体存储器件包括包括第一线，第二线和存储单元的存储单元阵列，每个存储单元包括可变电阻器，并且每个存储器单元连接在第一线路和第二线路中的一个之间，并且控制器 电路，被配置为执行向连接到所选择的存储器单元的所选择的第一线施加第一电压并将具有低于所述第一电压的电压值的第二电压施加到连接到所选择的存储器单元的所选择的第二线的电压施加操作。 控制电路被配置为从多个不同的电压值中选择第二电压的电压值并输出第二电压。

公开(公告)号：US20130028028A1

公开(公告)日：2013-01-31

申请号：US13417494

申请日：2012-03-12

申请人： Junya MATSUNAMI

发明人： Junya MATSUNAMI

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11521

摘要： A plurality of element isolation insulating films are formed in a semiconductor substrate in a memory cell array and have a first direction as a long direction. A plurality of element formation regions are formed isolated by the element isolation insulating films. A memory string is formed in each of the element formation regions. A plurality of element formation region groups are each configured by the element formation regions. In a memory cell array, in a second direction orthogonal to the first direction, a spacing between the element formation region groups is configured larger than a spacing between the element formation regions in each of the element formation region groups. A control circuit executes a write operation on the memory cell array on an element formation region group basis.

摘要翻译： 在存储单元阵列中的半导体衬底中形成多个元件隔离绝缘膜，并且具有作为长方向的第一方向。 通过元件隔离绝缘膜形成多个元件形成区域。 在每个元件形成区域中形成存储器串。 多个元件形成区域组由元件形成区域构成。 在存储单元阵列中，在与第一方向正交的第二方向上，元件形成区域组之间的间隔被构造为大于元件形成区域组中的元件形成区域之间的间隔。 控制电路在元件形成区域组上对存储单元阵列执行写入操作。

公开(公告)号：US20120140558A1

公开(公告)日：2012-06-07

申请号：US13239572

申请日：2011-09-22

申请人： Junya MATSUNAMI

发明人： Junya MATSUNAMI

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A control circuit applies a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line. The circuit then performs a verify read operation to confirm whether the data write to the 1-page memory cells is completed. According to the result of the verify read operation, a step-up operation is performed out to raise the write pulse voltage by a step-up voltage. The control circuit changes the amount of the step-up voltage according to a distribution width of a first threshold voltage distribution generated in process of the write operation to the memory cells.

摘要翻译： 控制电路对所选字线施加写入脉冲电压，以对所选字线的1页存储单元执行写入操作。 然后，电路执行验证读取操作，以确认写入1页存储单元的数据是否完成。 根据验证读取操作的结果，执行升压操作以通过升压电压提高写入脉冲电压。 控制电路根据写操作在存储单元中产生的第一阈值电压分布的分布宽度来改变升压电压的量。

公开(公告)号：US20110108901A1

公开(公告)日：2011-05-12

申请号：US12886225

申请日：2010-09-20

申请人： Junya MATSUNAMI ,  Hiroyuki Kutsukake

发明人： Junya MATSUNAMI ,  Hiroyuki Kutsukake

IPC分类号： H01L27/108 ,  H01L21/8246

CPC分类号： H01L27/11524 ,  H01L27/11519 ,  H01L27/11521

摘要： Device isolation/insulation films each have a first height within a first area and a second height higher than the first height within a second area. At least the device isolation/insulation films adjacent to a contact diffusion region exist in the second area, and the device isolation/insulation films adjacent to memory transistors exist in the first area. The device isolation/insulation films are implanted with an impurity of a first conductivity type, and device formation regions each have a diffusion region of the first conductivity type, the diffusion region being formed by diffusion of the impurity of the first conductivity type from the device isolation/insulation films.

摘要翻译： 设备隔离/绝缘膜各自在第一区域内具有第一高度，并且在第二区域内具有高于第一高度的第二高度。 至少与接触扩散区相邻的器件隔离/绝缘膜存在于第二区域中，并且在第一区域中存在与存储晶体管相邻的器件隔离/绝缘膜。 器件隔离/绝缘膜被注入第一导电类型的杂质，器件形成区域各自具有第一导电类型的扩散区域，扩散区域通过从器件扩散第一导电类型的杂质形成 隔离/绝缘膜。