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1.发明申请RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US20160118117A1
公开(公告)日：2016-04-28
申请号：US14716558
申请日：2015-05-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYUN-KOOK PARK , CHI-WEON YOON , YEONG-TAEK LEE
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C11/56 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2013/0088
Abstract: A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells connected to a first bit line, selecting one or more second memory cells connected to a second bit line, and simultaneously performing a reset write operation on the first and second memory cells using a first write driver.
Abstract translation: 一种操作具有多个字线和多个位线的电阻式存储器件的方法包括选择连接到第一位线的一个或多个第一存储器单元，选择连接到第二位线的一个或多个第二存储器单元，以及 使用第一写入驱动器同时对所述第一和第二存储器单元执行复位写入操作。
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2.发明申请RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT 有权电阻式存储器件及其运行方法降低泄漏电流公开(公告)号：US20160093376A1
公开(公告)日：2016-03-31
申请号：US14683269
申请日：2015-04-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YONG-KYU LEE , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , HYUN-KOOK PARK , HYO-JIN KWON
IPC: G11C13/00
CPC classification number: G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。
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Patent Agency Ranking
公开(公告)号：US20160027510A1
公开(公告)日：2016-01-28
申请号：US14697244
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YONG-KYU LEE , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , HYUN-KOOK PARK , HYO-JIN KWON
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择存储单元的第二信号线根据执行编程循环的次数而改变。
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4.发明申请公开(公告)号：US20180150261A1
公开(公告)日：2018-05-31
申请号：US15676778
申请日：2017-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WAN NAM , DAE-SEOK BYEON , CHI-WEON YOON , HAE-SUK SHIN
IPC: G06F3/06
CPC classification number: G11C16/06 , G06F3/0604 , G06F3/0616 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F3/0688
Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.
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公开(公告)号：US20160196876A1
公开(公告)日：2016-07-07
申请号：US14979947
申请日：2015-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YONG-KYU LEE , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C5/063 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。 写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。 电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。 电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于 检测到的节点电压。
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公开(公告)号：US20160042811A1
公开(公告)日：2016-02-11
申请号：US14743521
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYO-JIN KWON , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , YONG-KYU LEE , HYUN-KOOK PARK
CPC classification number: G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Abstract translation: 电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。 多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。 不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。
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公开(公告)号：US20160027508A1
公开(公告)日：2016-01-28
申请号：US14631182
申请日：2015-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YONG-KYU LEE , DAE-SEOK BYEON , HYO-JIN KWON , HYUN-KOOK PARK , CHI-WEON YOON , YEONG-TAEK LEE
IPC: G11C13/00
CPC classification number: G11C13/0033 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。
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