SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开

    公开(公告)号:US20230363142A1

    公开(公告)日:2023-11-09

    申请号:US18130769

    申请日:2023-04-04

    IPC分类号: H10B12/00

    CPC分类号: H10B12/31 H10B12/033

    摘要: A semiconductor memory device includes an interlayer insulating layer, a plurality of first contact pads embedded in the interlayer insulating layer, a plurality of first work function adjustment patterns embedded in the interlayer insulating layer and disposed on the plurality of first contact pads, and a plurality of lower electrodes disposed on the plurality of first work function adjustment patterns.

    Semiconductor devices
    2.
    发明授权

    公开(公告)号:US12057470B2

    公开(公告)日:2024-08-06

    申请号:US17809727

    申请日:2022-06-29

    IPC分类号: H01L21/00 H01L49/02 H10B12/00

    摘要: A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

    CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

    公开(公告)号:US20240105765A1

    公开(公告)日:2024-03-28

    申请号:US18461408

    申请日:2023-09-05

    IPC分类号: H01G4/30 H10B12/00

    摘要: A capacitor structure includes a first lower conductive pattern, a first capacitor, a first upper conductive pattern, a second lower conductive pattern, a second capacitor and a second upper conductive pattern. The first capacitor includes first lower electrodes, first upper electrodes and first dielectric structures. Each of the first dielectric structures are disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes. The first upper conductive pattern is formed on and is electrically connected to the first upper electrodes. The second lower conductive pattern is spaced apart from the first lower conductive pattern disposed on the substrate. The second capacitor includes second lower electrodes, second upper electrodes and second dielectric structures. The second upper conductive pattern is formed on and is electrically connected to the second upper electrodes. The first and second conductive patterns are electrically insulated from each other.

    SEMICONDUCTOR DEVICE
    5.
    发明公开

    公开(公告)号:US20230290811A1

    公开(公告)日:2023-09-14

    申请号:US18052562

    申请日:2022-11-03

    IPC分类号: H01L29/00

    CPC分类号: H01L28/56 H01L28/60

    摘要: A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are stacked in a first direction. The dielectric layer includes a first dielectric layer, a second dielectric layer stacked on the first dielectric layer in the first direction, and a first impurity provided in the first dielectric layer. The first dielectric layer includes a ferroelectric material, and the second dielectric layer includes an anti-ferroelectric material.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开

    公开(公告)号:US20240321943A1

    公开(公告)日:2024-09-26

    申请号:US18601032

    申请日:2024-03-11

    IPC分类号: H10B12/00

    摘要: A semiconductor memory device includes an upper electrode, a lower electrode, an anti-ferroelectric layer disposed between the upper electrode and the lower electrode and including an anti-ferroelectric, an oxide layer disposed on a first surface of the anti-ferroelectric layer and including a high dielectric material, and a metal oxide layer disposed on a second surface of the anti-ferroelectric layer opposite to the first surface. A thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the anti-ferroelectric layer.

    SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20240292596A1

    公开(公告)日:2024-08-29

    申请号:US18489189

    申请日:2023-10-18

    IPC分类号: H10B12/00

    CPC分类号: H10B12/315 H10B12/033

    摘要: A semiconductor device includes a lower structure, a capacitor on the lower structure, the capacitor including a first bottom electrode, which is extended in a direction perpendicular to a bottom surface of the lower structure, and a second bottom electrode, which is provided on the first bottom electrode, a bottom supporting pattern supporting the first bottom electrode, and a top supporting pattern provided on the bottom supporting pattern to support the first bottom electrode. The first bottom electrode includes a first material, and the second bottom electrode may include a second material. A work function of the second material is greater than a work function of the first material.

    DEPOSITION SYSTEM AND PROCESSING SYSTEM
    8.
    发明公开

    公开(公告)号:US20240209495A1

    公开(公告)日:2024-06-27

    申请号:US18425048

    申请日:2024-01-29

    摘要: A deposition system, includes: a reaction chamber; a first gas supply unit supplying a first precursor in a liquid state stored in a first main tank to the reaction chamber in a gaseous state; a reactant supply unit supplying a reactant to the reaction chamber; and an exhaust unit discharging an exhaust material, wherein the first gas supply unit includes a first sub tank, a first liquid mass flow controller, and a first vaporizer, the first precursor is supplied to the reaction chamber by passing through the first sub tank, the first liquid mass flow controller, and the first vaporizer, a first automatic refill system operates to periodically fill the first sub tank with the liquid first precursor stored in the first main tank, and the exhaust unit comprises a processing chamber, a pump, and a scrubber to which a plasma pretreatment system is applied.

    SEMICONDUCTOR DEVICE
    10.
    发明公开

    公开(公告)号:US20240008254A1

    公开(公告)日:2024-01-04

    申请号:US18116071

    申请日:2023-03-01

    IPC分类号: H10B12/00

    CPC分类号: H10B12/315 H10B12/033

    摘要: A semiconductor device includes a substrate, a lower electrode above the substrate, the lower electrode extending in a vertical direction, a support surrounding a side wall of the lower electrode and supporting the lower electrode, a dielectric layer on the lower electrode and the support, and an upper electrode on the dielectric layer, wherein the lower electrode includes a base electrode layer and an insertion layer, the base electrode layer containing a halogen element, and the insertion layer containing carbon, and the insertion layer is inserted in a portion of the lower electrode, the portion of the lower electrode being adjacent to the support and the dielectric layer.