Abstract:
A capacitor structure may include a lower electrode on a substrate, a dielectric layer on the substrate, and an upper electrode on the dielectric layer. The lower electrode may include a metal nitride having a chemical formula of M1Ny (M1 is a first metal, and y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), the metal oxide having a chemical formula of M2Ox (M2 is a second metal, and x is a positive real number). A maximum value of a detection amount of nitrogen (N) in the dielectric layer may be greater than a maximum value of a detection amount of nitrogen (N) in the lower electrode.
Abstract:
A deposition system, includes: a reaction chamber; a first gas supply unit supplying a first precursor in a liquid state stored in a first main tank to the reaction chamber in a gaseous state; a reactant supply unit supplying a reactant to the reaction chamber; and an exhaust unit discharging an exhaust material, wherein the first gas supply unit includes a first sub tank, a first liquid mass flow controller, and a first vaporizer, the first precursor is supplied to the reaction chamber by passing through the first sub tank, the first liquid mass flow controller, and the first vaporizer, a first automatic refill system operates to periodically fill the first sub tank with the liquid first precursor stored in the first main tank, and the exhaust unit comprises a processing chamber, a pump, and a scrubber to which a plasma pretreatment system is applied.
Abstract:
A method of operating a storage device which communicates with a host device includes allocating a plurality of unit zone regions each having a unit zone size, each of the plurality of unit zone regions being mapped to at least one corresponding memory blocks among a plurality of memory blocks in the storage device and supporting a sequential write in compliance with a zoned namespace (ZNS) standard, receiving a first request indicating an allocation operation of a first zoned namespace in compliance with the ZNS standard from the host device, determining a first mapping ratio by dividing a first zone size of the first zoned namespace by the unit zone size, based on the first request, and storing the first mapping ratio in a zone metadata table of the storage device.
Abstract:
A deposition system, includes: a reaction chamber; a first gas supply unit supplying a first precursor in a liquid state stored in a first main tank to the reaction chamber in a gaseous state; a reactant supply unit supplying a reactant to the reaction chamber; and an exhaust unit discharging an exhaust material, wherein the first gas supply unit includes a first sub tank, a first liquid mass flow controller, and a first vaporizer, the first precursor is supplied to the reaction chamber by passing through the first sub tank, the first liquid mass flow controller, and the first vaporizer, a first automatic refill system operates to periodically fill the first sub tank with the liquid first precursor stored in the first main tank, and the exhaust unit comprises a processing chamber, a pump, and a scrubber to which a plasma pretreatment system is applied.
Abstract:
A capacitor structure may include a lower electrode on a substrate, a dielectric layer on the substrate, and an upper electrode on the dielectric layer. The lower electrode may include a metal nitride having a chemical formula of M1Ny (M1 is a first metal, and y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), the metal oxide having a chemical formula of M2Ox (M2 is a second metal, and x is a positive real number). A maximum value of a detection amount of nitrogen (N) in the dielectric layer may be greater than a maximum value of a detection amount of nitrogen (N) in the lower electrode.
Abstract:
A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.
Abstract:
An operating method of a data storge device including a buffer memory, a non-volatile memory, and a controller, includes receiving, from a host, an encryption request for data stored in the buffer memory, and performing an encryption operation in response to the encryption request, wherein the performing of the encryption operation comprises performing a program operation, the performing of the program operation comprises receiving a physical address of a buffer region of the non-volatile memory, generating encrypted data by causing an encryption module included in the controller to be in an on state to encrypt the data stored in the buffer memory, and programming the encrypted data in the buffer region of the non-volatile memory based on the physical address.
Abstract:
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.
Abstract:
A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.
Abstract:
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.