HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高电子移动性晶体管及其制造方法

    公开(公告)号:US20140327043A1

    公开(公告)日:2014-11-06

    申请号:US14085121

    申请日:2013-11-20

    Abstract: Provided are a high electron mobility transistor (HEMT) and a method of manufacturing the HEMT. The HEMT includes: a channel layer comprising a first semiconductor material; a channel supply layer comprising a second semiconductor material and generating two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode separated from each other in the channel supply layer; at least one depletion forming unit that is formed on the channel supply layer and forms a depletion region in the 2DEG; at least one gate electrode that is formed on the at least one depletion forming unit; at least one bridge that connects the at least one depletion forming unit and the source electrode; and a contact portion that extends from the at least one bridge under the source electrode.

    Abstract translation: 提供高电子迁移率晶体管(HEMT)和制造HEMT的方法。 HEMT包括:包含第一半导体材料的沟道层; 沟道供应层,包括第二半导体材料并在沟道层中产生二维电子气(2DEG); 在所述沟道供给层中彼此分离的源电极和漏电极; 至少一个耗尽形成单元,其形成在所述沟道供应层上并在所述2DEG中形成耗尽区; 形成在所述至少一个耗尽形成单元上的至少一个栅电极; 连接所述至少一个耗尽形成单元和所述源电极的至少一个桥; 以及从所述源电极下方的所述至少一个桥延伸的接触部。

    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高电子移动性晶体管及其制造方法

    公开(公告)号:US20140151749A1

    公开(公告)日:2014-06-05

    申请号:US14091822

    申请日:2013-11-27

    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a part of the channel supply layer between the source electrode and the drain electrode; a first depletion-forming layer between the gate electrode and the channel supply layer; and a at least one second depletion-forming layer on the channel supply layer between the gate electrode and the drain electrode. The at least one second depletion-forming layer is electrically connected to the source electrode.

    Abstract translation: 根据示例性实施例,高电子迁移率晶体管(HEMT)包括沟道层; 通道层上的通道供应层; 在所述沟道层和所述沟道供给层之一上彼此隔开的源电极和漏电极; 源电极和漏电极之间的沟道供给层的一部分上的栅电极; 在栅电极和沟道供应层之间的第一耗尽层; 以及在栅电极和漏电极之间的沟道供应层上的至少一个第二耗尽层。 所述至少一个第二耗尽形成层电连接到所述源电极。

    POWER DEVICE CHIP AND METHOD OF MANUFACTURING THE POWER DEVICE CHIP
    3.
    发明申请
    POWER DEVICE CHIP AND METHOD OF MANUFACTURING THE POWER DEVICE CHIP 有权
    电源设备芯片和制造电源设备芯片的方法

    公开(公告)号:US20140291728A1

    公开(公告)日:2014-10-02

    申请号:US14224769

    申请日:2014-03-25

    CPC classification number: H01L29/778 H01L29/1608 H01L29/402 H01L29/7787

    Abstract: According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of the plurality of sectors. The first pad is connected to first electrodes of the plurality of unit power devices, and the second pad is connected to second electrodes of the plurality of unit power devices. The unit power devices may be diodes. The power device chip may further include third electrodes in the plurality of unit power devices, and a third pad may be connected to the third electrodes. In this case, the unit power devices may be high electron mobility transistors (HEMTs). Pad parts connected to defective sectors may be excluded from bonding.

    Abstract translation: 根据示例性实施例,功率器件芯片包括分为多个扇区的多个单位功率器件,第一焊盘和第二焊盘。 第一和第二焊盘中的至少一个被分成等于多个扇区的数量的多个焊盘部分。 第一焊盘连接到多个单元功率器件的第一电极,第二焊盘连接到多个单元功率器件的第二电极。 单元功率器件可以是二极管。 功率器件芯片还可以包括多个单位功率器件中的第三电极,并且第三焊盘可以连接到第三电极。 在这种情况下,单位功率器件可以是高电子迁移率晶体管(HEMT)。 连接到缺陷扇区的焊盘部件可能被排除在接合之外。

    HIGH ELECTRON MOBILITY TRANSISTOR
    4.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR 有权
    高电子移动晶体管

    公开(公告)号:US20140027779A1

    公开(公告)日:2014-01-30

    申请号:US13953165

    申请日:2013-07-29

    Abstract: According to example embodiments, a high electron mobility transistor includes: a channel layer including a 2-dimensional electron gas (2DEG); a contact layer on the channel layer; a channel supply layer on the contact layer; a gate electrode on a portion of the channel layer; and source and drain electrodes on at least one of the channel layer, the contact layer, and the channel supply layer. The contact layer is configured to form an ohmic contact on the channel layer. The contact layer is n-type doped and contains a Group III-V compound semiconductor. The source electrode and the drain electrode are spaced apart from opposite sides of the gate electrode.

    Abstract translation: 根据示例性实施例,高电子迁移率晶体管包括:包括二维电子气(2DEG)的沟道层; 沟道层上的接触层; 接触层上的沟道供应层; 沟道层的一部分上的栅电极; 以及在沟道层,接触层和沟道供应层中的至少一个上的源极和漏极。 接触层被配置为在沟道层上形成欧姆接触。 接触层为n型掺杂并含有III-V族化合物半导体。 源电极和漏电极与栅电极的相对侧间隔开。

    MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    5.
    发明申请
    MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
    磁记忆体装置及其操作方法

    公开(公告)号:US20130294151A1

    公开(公告)日:2013-11-07

    申请号:US13939879

    申请日:2013-07-11

    Inventor: In-jun HWANG

    Abstract: A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past both ends of the free layer. The magnetic memory device further includes a switching element connected to a second surface of the free layer. Another magnetic memory device includes: a first reference layer having a first magnetic domain wall; a second reference layer having a second magnetic domain wall; and a memory structure between the first and second reference layers. The memory structure includes: a first free layer adjacent to the first reference layer; a second free layer adjacent to the second reference layer; and a switching element between the first and second free layers.

    Abstract translation: 磁存储器件包括:用于存储信息的自由层; 以及设置在自由层的第一表面上的参考层。 参考层包括至少两个磁畴和至少两个磁畴之间的磁畴壁。 参考层延伸经过自由层的两端。 磁存储器件还包括连接到自由层的第二表面的开关元件。 另一磁存储器件包括:具有第一磁畴壁的第一参考层; 具有第二磁畴壁的第二参考层; 以及第一和第二参考层之间的存储器结构。 存储器结构包括:与第一参考层相邻的第一自由层; 与第二参考层相邻的第二自由层; 以及第一和第二自由层之间的开关元件。

    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高电子移动性晶体管及其制造方法

    公开(公告)号:US20130234207A1

    公开(公告)日:2013-09-12

    申请号:US13714957

    申请日:2012-12-14

    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes: stack including a buffer layer, a channel layer containing a two dimensional electron gas (2DEG) channel, and a channel supply layer sequentially stacked on each other, the stack defining a first hole and a second hole that are spaced apart from each other. A first electrode, a second electrode, and third electrode are spaced apart from each other along a first surface of the channel supply layer. A first pad is on the buffer layer and extends through the first hole of the stack to the first electrode. A second pad is on the buffer layer and extends through the second hole of the stack to the second electrode. A third pad is under the stack and electrically connected to the third electrode.

    Abstract translation: 根据示例性实施例,高电子迁移率晶体管(HEMT)包括:包括缓冲层的堆叠,包含二维电子气体(2DEG)通道的沟道层和相互堆叠的沟道供应层,所述堆叠限定 第一孔和彼此间隔开的第二孔。 第一电极,第二电极和第三电极沿着沟道供应层的第一表面彼此间隔开。 第一焊盘在缓冲层上并且延伸穿过堆叠的第一孔至第一电极。 第二焊盘位于缓冲层上并且延伸穿过堆叠的第二孔至第二电极。 第三焊盘在堆叠下方并电连接到第三电极。

    METHOD OF REDUCING CURRENT COLLAPSE OF POWER DEVICE
    9.
    发明申请
    METHOD OF REDUCING CURRENT COLLAPSE OF POWER DEVICE 有权
    降低功率器件电流的方法

    公开(公告)号:US20140266400A1

    公开(公告)日:2014-09-18

    申请号:US13973379

    申请日:2013-08-22

    CPC classification number: H03K17/063 H03K17/161

    Abstract: According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the control electrode is electrically separated from a source electrode, a drain electrode, and a gate electrode of the power device. The control voltage is separately applied to the control electrode. The method may include applying a negative control voltage to the control electrode prior to applying a gate voltage to the gate electrode.

    Abstract translation: 根据示例实施例,一种操作功率器件的方法包括将控制电压施加到功率器件的控制电极,其中控制电极与功率器件的源电极,漏电极和栅电极电分离 。 控制电压分别施加到控制电极。 该方法可以包括在向栅电极施加栅极电压之前向控制电极施加负控制电压。

    HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高电子移动晶体管及其制造方法

    公开(公告)号:US20140097470A1

    公开(公告)日:2014-04-10

    申请号:US13910417

    申请日:2013-06-05

    Abstract: According to example embodiments, a HEMT includes a channel supply layer on a channel layer, a p-type semiconductor structure on the channel supply layer, a gate electrode on the p-type semiconductor structure, and source and drain electrodes spaced apart from two sides of the gate electrode respectively. The channel supply layer may have a higher energy bandgap than the channel layer. The p-type semiconductor structure may have an energy bandgap that is different than the channel supply layer. The p-type semiconductor structure may include a hole injection layer (HIL) on the channel supply layer and be configured to inject holes into at least one of the channel layer and the channel supply in an on state. The p-type semiconductor structure may include a depletion forming layer on part of the HIL. The depletion forming layer may have a dopant concentration that is different than the dopant concentration of the HIL.

    Abstract translation: 根据示例性实施例,HEMT包括在沟道层上的沟道供应层,沟道供应层上的p型半导体结构,p型半导体结构上的栅电极以及与两侧隔开的源极和漏极 的栅电极。 通道供应层可以具有比沟道层更高的能量带隙。 p型半导体结构可以具有与沟道供给层不同的能量带隙。 p型半导体结构可以包括在沟道供应层上的空穴注入层(HIL),并且被配置为在导通状态下将空穴注入至少一个沟道层和沟道电源。 p型半导体结构可以在HIL的一部分上包括耗尽形成层。 耗尽形成层可以具有不同于HIL的掺杂剂浓度的掺杂剂浓度。

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