公开(公告)号：US20210091045A1

公开(公告)日：2021-03-25

申请号：US16877169

申请日：2020-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNYEONG HEO ,  JAE-EUN LEE ,  YEONGKWON KO ,  DONGHOON WON

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

公开(公告)号：US20170293219A1

公开(公告)日：2017-10-12

申请号：US15442780

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-KIL YUN ,  SUNGHOON KIM ,  JAE-EUN LEE ,  HYANGJA YANG

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: A method for verifying mask data in a computing device includes receiving layout data, receiving mask data, determining an interaction number between a pattern corresponding to the layout data and a pattern corresponding to the mask data, and detecting an error of the mask data based on the interaction number.

公开(公告)号：US20170047345A1

公开(公告)日：2017-02-16

申请号：US15335482

申请日：2016-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-EUN LEE ,  SUNGHOON KIM

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L24/05 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2924/00012

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.

Abstract translation: 非易失性存储器件包括包括多个存储单元的存储单元阵列，第一金属层，被配置为控制存储单元阵列的外围电路，第二金属层和衬垫。 第一金属层设置在存储单元阵列上，并且包括连接到存储单元阵列的多个单元区域互连。 第二金属层设置在外围电路上，并且包括连接外围电路和多个单元区域互连的多个周边区域互连。 焊盘设置在第二金属层上，并在设备的操作期间与外围电路交换数据，地址或命令。 第二金属层相对于器件的衬底低于第一金属层。

公开(公告)号：US20160307632A1

公开(公告)日：2016-10-20

申请号：US15049526

申请日：2016-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-EUN LEE ,  SUNGHOON KIM

IPC: G11C16/14 ,  H01L23/528 ,  H01L21/768 ,  G11C16/04 ,  H01L23/532 ,  H01L27/115 ,  H01L23/522

CPC classification number: G11C16/14 ,  G11C5/025 ,  G11C16/0483 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53271 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.

Abstract translation: 提供了包括周边区域和堆叠在其上的单元区域的半导体器件及其制造方法。 半导体器件可以包括包括下基板和设置在其上的外围电路的周边区域，以及包括设置在其上的上基板和单元阵列的单元区域。 单元区域可以堆叠在周边区域上。 当从周边区域向单元区域施加操作信号时，外围区域和单元区域的至少一部分可以用作施加有接地信号的接地图案，从而处于电接地状态。