公开(公告)号：US12148708B2

公开(公告)日：2024-11-19

申请号：US18141568

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/552 ,  H01L23/66 ,  H01L25/16 ,  H01Q1/38

Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.

公开(公告)号：US20220005793A1

公开(公告)日：2022-01-06

申请号：US17155260

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam KANG ,  Sang Kyu Lee ,  Jin Gu Kim ,  Yong Koon Lee

IPC: H01L25/10 ,  H01L25/00

Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer.

公开(公告)号：US11062999B2

公开(公告)日：2021-07-13

申请号：US16570055

申请日：2019-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

公开(公告)号：US20200185815A1

公开(公告)日：2020-06-11

申请号：US16410853

申请日：2019-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Jin Su Kim

IPC: H01Q1/22 ,  H01Q9/16 ,  H01Q1/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: An antenna module includes an antenna substrate having a first surface and a second surface disposed to oppose each other, and including a substrate wiring layer having a first antenna pattern positioned in a first region, a second antenna pattern disposed in a second region adjacent to one side, and first and second feed patterns connected to the first and second antenna patterns, respectively; and a semiconductor package including a connection structure disposed on the second surface except for an area overlapping with the second region of the antenna substrate and redistribution layers electrically connected to the substrate wiring layer, and at least one semiconductor chip having connection pads connected to the redistribution layers. A region overlapping with the second feed pattern in each of the plurality of redistribution layers is provided as an opened region.

公开(公告)号：US11676907B2

公开(公告)日：2023-06-13

申请号：US17353074

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/66 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01Q1/38 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/82101 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

公开(公告)号：US11670623B2

公开(公告)日：2023-06-06

申请号：US17155260

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Sang Kyu Lee ,  Jin Gu Kim ,  Yong Koon Lee

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/50 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer.

公开(公告)号：US10903548B2

公开(公告)日：2021-01-26

申请号：US16410853

申请日：2019-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Jin Su Kim

IPC: H01Q1/22 ,  H01Q1/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q9/16

Abstract: An antenna module includes an antenna substrate having a first surface and a second surface disposed to oppose each other, and including a substrate wiring layer having a first antenna pattern positioned in a first region, a second antenna pattern disposed in a second region adjacent to one side, and first and second feed patterns connected to the first and second antenna patterns, respectively; and a semiconductor package including a connection structure disposed on the second surface except for an area overlapping with the second region of the antenna substrate and redistribution layers electrically connected to the substrate wiring layer, and at least one semiconductor chip having connection pads connected to the redistribution layers. A region overlapping with the second feed pattern in each of the plurality of redistribution layers is provided as an opened region.

公开(公告)号：US10896884B2

公开(公告)日：2021-01-19

申请号：US16281819

申请日：2019-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Jin Su Kim

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/538 ,  H01L23/495 ,  H01Q1/22

Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.

公开(公告)号：US10763217B2

公开(公告)日：2020-09-01

申请号：US16282638

申请日：2019-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Jin Su Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.