Abstract:
A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).
Abstract:
The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services, or the like.A method for issuing an access token of a device by a control point is provided. The method includes transmitting a search request message to the device, receiving, from the device, a search response message including first information indicating a type of the device, requesting access token issuance to the device using first information and second information, the second information including additional information about the device, and receiving the access token from the device. The second information may include model information about the device.
Abstract:
An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.
Abstract:
A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).
Abstract:
An apparatus of a Digital-to-Analog Converter (DAC) is provided. The apparatus includes a logic circuit for performing a logical operation based on a combination of bit values b0 through bN-1 of a digital code, and a plurality of switches for controlling an output state of a plurality of current cells based on an output of the logical operation, wherein the plurality of the current cells respectively output currents under a control of respective ones of the plurality of switches.
Abstract:
An analog amplifier for recovering an abnormal operation of a common-mode feedback is provided. An analog variable amplifier includes a first input transistor and a second input transistor, a first output transistor and a second output transistor, a third transistor and a fourth transistor, a first current source, a fifth transistor and a sixth transistor, and a second current source. The first input transistor and the second input transistor amplify a bias current depending on a magnitude of a first input voltage and a second input voltage. The first output transistor and the second output transistor output the amplified bias current. The third transistor and the fourth transistor receive an output voltage of the first output transistor as an input and amplifying the received output voltage. The first current source provides a predetermined current between the first output transistor and the third transistor.
Abstract:
An analog baseband filter apparatus for a multi-mode and multi-band wireless transceiver and a method for controlling the analog baseband filter apparatus are provided. The analog baseband filter apparatus includes a plurality of Radio Frequency (RF) units, each of the plurality of RF units being for receiving RF signals of one of a plurality of frequency bands and outputting baseband signals, a plurality of filter blocks for filtering and amplifying the baseband signals, and a switching unit for connecting at least two of the plurality of RF units to at least one of the plurality of filter blocks according to a selected communication mode, wherein the at least one of the plurality of filter blocks is configured to be connected to a capacitor region of an adjacent filter block from among the plurality of filter blocks.
Abstract:
An amplifier circuit is provided. The amplifier circuit includes an operational amplifier, a feedback resistor for changing gain and cutoff frequency characteristics of the operational amplifier, and a feedback variable capacitor for changing the cutoff frequency characteristics of the operational amplifier, wherein a capacitance of the feedback variable capacitor increases exponentially according to a digital control code, and the cutoff frequency of the operational amplifier is inversely proportional to the capacitance of the feedback variable capacitor and varies linearly on a logarithmic scale.
Abstract:
An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality.
Abstract:
The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals.