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公开(公告)号:US20170133370A1
公开(公告)日:2017-05-11
申请号:US15409033
申请日:2017-01-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Gun YOU , Hyung-Jong LEE , Sung-Min KIM , Chong-Kwang CHANG
IPC: H01L27/088 , H01L29/06 , H01L23/532 , H01L23/485 , H01L23/528
CPC classification number: H01L27/0886 , H01L23/485 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L29/0649
Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
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公开(公告)号:US20210280682A1
公开(公告)日:2021-09-09
申请号:US17329240
申请日:2021-05-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Gun YOU , Myung-Yoon UM , Young-Joon PARK , Jeong-Hyo LEE , Ji-Yong HA , Jun-sun HWANG
IPC: H01L29/423 , H01L21/28 , H01L29/40 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/8234 , H01L27/092 , H01L21/8238 , H01L27/088
Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.
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公开(公告)号:US20170110569A1
公开(公告)日:2017-04-20
申请号:US15292144
申请日:2016-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chong-Kwang CHANG , Young-Mook OH , Hak-Yoon AHN , Jung-Gun YOU , Gi-Gwan PARK , Baik-Min SUNG
IPC: H01L29/78 , H01L23/528 , H01L21/768 , H01L23/522
CPC classification number: H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53295 , H01L2029/7858
Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.
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公开(公告)号:US20190123159A1
公开(公告)日:2019-04-25
申请号:US16220028
申请日:2018-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Gun YOU , Myung-Yoon UM , Young-Joon PARK , Jeong-Hyo LEE , Ji-Yong HA , Jun-sun HWANG
IPC: H01L29/423 , H01L21/28 , H01L21/8234 , H01L29/40 , H01L29/66 , H01L21/762 , H01L29/78
Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.
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公开(公告)号:US20180248035A1
公开(公告)日:2018-08-30
申请号:US15670154
申请日:2017-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung-Il PARK , Beom-Jin PARK , Yun-Il LEE , Jung-Gun YOU , Dong-Hun LEE
IPC: H01L29/78 , H01L29/788 , H01L27/11556 , H01L27/092 , H01L29/66 , H01L29/423
CPC classification number: H01L29/7827 , H01L21/823418 , H01L21/823487 , H01L27/0738 , H01L27/088 , H01L27/0924 , H01L27/11556 , H01L27/1203 , H01L29/4232 , H01L29/66666 , H01L29/7889 , H01L2027/11866
Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.
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公开(公告)号:US20180226404A1
公开(公告)日:2018-08-09
申请号:US15944956
申请日:2018-04-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Gun YOU , Hyung-Jong LEE , Sung-Min KIM , Chong-Kwang CHANG
IPC: H01L27/088 , H01L23/528 , H01L23/532 , H01L29/06 , H01L23/485
CPC classification number: H01L27/0886 , H01L23/485 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L29/0649
Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
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公开(公告)号:US20170062420A1
公开(公告)日:2017-03-02
申请号:US15222300
申请日:2016-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Gun YOU , Dae-Lim KANG , Myung-Yoon UM , Jeong-Hyo LEE , Jae-Yup CHUNG , Jun-Sun HWANG , Bo-Cheol JEONG
IPC: H01L27/088 , H01L29/40 , H01L29/423
CPC classification number: H01L27/0886 , H01L21/823481 , H01L29/0847 , H01L29/408 , H01L29/42376 , H01L29/4238
Abstract: A semiconductor device including a first fin pattern and a second fin pattern which have respective short sides facing each other and are separated from each other, a first field insulating layer which is around the first fin pattern and the second fin pattern, a second field insulating layer and a third field insulating layer which are between the first fin pattern and the second fin pattern, a first gate which is formed on the first fin pattern to intersect the first fin pattern, a second gate which is formed on the second field insulating layer, and a third gate which is formed on the third field insulating layer, wherein upper surfaces of the second and third field insulating layers protrude further upward than an upper surface of the first field insulating layer, and a distance between the first gate and the second gate is equal to a distance between the second gate and the third gate.
Abstract translation: 一种半导体器件,包括:第一鳍状图案和第二鳍状图案,其具有彼此相对的彼此分离的短边;第一场绝缘层,其围绕第一鳍状图案和第二鳍状图案;第二场隔绝 层和第三场绝缘层,位于第一鳍状图案和第二鳍状图案之间,形成在第一鳍状图案上以与第一鳍状图案相交的第一栅极,形成在第二场绝缘层上的第二栅极 以及形成在第三场绝缘层上的第三栅极,其中第二和第三场绝缘层的上表面比第一场绝缘层的上表面进一步向上突出,并且第一栅极和第二栅极之间的距离 栅极等于第二栅极和第三栅极之间的距离。
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公开(公告)号:US20170047326A1
公开(公告)日:2017-02-16
申请号:US15155744
申请日:2016-05-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Gun YOU , Ki-Il Kim , Gi-Gwan Park , Sug-Hyun Sung , Myung-Yoon Um
IPC: H01L27/088 , H01L29/78 , H01L29/06
CPC classification number: H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L27/0207 , H01L29/0649 , H01L29/0657 , H01L29/7851 , H01L29/7853 , H01L29/7854
Abstract: A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.
Abstract translation: 半导体器件包括:衬底,包括第一沟槽,由第一沟槽限定的衬底上的第一鳍图案,衬底上的栅电极和衬底上的场绝缘层。 第一鳍状图案包括下部的上部。 第一翅片图案包括彼此相对的第一侧壁和第二侧壁。 第一侧壁沿着第一鳍片图案的下部是凹形的。 第二侧壁沿着第一翅片图案的下部倾斜。 场绝缘层围绕第一鳍片图案的下部。 栅极电极围绕第一鳍片图案的上部。
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公开(公告)号:US20160141243A1
公开(公告)日:2016-05-19
申请号:US14712136
申请日:2015-05-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Gun YOU , Wei-Hua HSU , Choong-Ho LEE , Hyung-Jong LEE
IPC: H01L23/522 , H01L27/088 , H01L23/535 , H01L27/092
CPC classification number: H01L23/5226 , H01L21/823871 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor. The first contact includes a first work function control layer having a first thickness and a first conductive layer formed on the first work function control layer, the second contact includes a second work function control layer having a second thickness different from the first thickness and a second conductive layer formed on the second work function control layer, and the first contact and the second contact have different work functions.
Abstract translation: 提供半导体器件及其制造方法。 该半导体器件包括分别包括第一区域和第二区域的基板,分别形成在第一区域和第二区域上的第一晶体管和第二晶体管,形成在第一晶体管上的第一触点和形成在第一晶体管上的第二触点 第二晶体管。 第一触点包括具有第一厚度的第一功函数控制层和形成在第一功函数控制层上的第一导电层,第二触点包括具有不同于第一厚度的第二厚度的第二功函数控制层, 导电层形成在第二功函数控制层上,第一触点和第二触点具有不同的功能。
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