公开(公告)号：US20190138233A1

公开(公告)日：2019-05-09

申请号：US16057849

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KUI-YON MUN ,  YOUNG-WOOK KIM ,  WAN-SOO CHOI

IPC: G06F3/06

Abstract: A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.

公开(公告)号：US20240078027A1

公开(公告)日：2024-03-07

申请号：US18238819

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KUI-YON MUN ,  JOOYOUNG HWANG ,  Gyeongmin KIM ,  KEUNSAN PARK ,  JOON-WHAN BAE

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0679

Abstract: A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells, wherein the controller is further configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units from among a plurality of erase units included in the plurality of memory cells to be allocated to each of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, wherein the nonvolatile memory device includes a plurality of memory chips, wherein each memory chip of the plurality of memory chips includes a plurality of memory blocks, wherein each memory block of the plurality of memory blocks includes at least two erase units, and wherein the controller is further configured to select at least one erase unit from the each memory block to be allocated to a zone.

公开(公告)号：US20160034390A1

公开(公告)日：2016-02-04

申请号：US14875205

申请日：2015-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KUI-YON MUN ,  HWA SEOK OH

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0292 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/202 ,  G06F2212/7207 ,  G11C16/0483 ,  G11C16/22 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group corresponding to a page to be currently programmed, wherein the stored seed group is stored among a plurality of seed groups. Data to be programmed into the current page is randomizing by using the pseudo random number and the memory controller outputs the randomized data. A solid state drive (SSD) or other memory storage device such as a memory card includes the memory controller and includes a read only memory (ROM) storing the plurality of seed groups. The memory controller includes a micro-processor and a read only memory (ROM) storing executable code for causing the micro-processor to access the plurality of stored seed groups and to select a seed therefrom corresponding to a page to be currently programmed.

公开(公告)号：US20150193163A1

公开(公告)日：2015-07-09

申请号：US14660897

申请日：2015-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KUI-YON MUN ,  HEEWON LEE

IPC: G06F3/06 ,  G11C29/52 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/52

Abstract: Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred.

Abstract translation: 随机序列数据基于分配给所选择的存储器空间的种子顺序生成，并且所选择的存储器空间的访问请求片段中的一个与顺序生成的随机序列数据逻辑组合以传送访问请求片段。 迭代执行顺序生成和逻辑组合，直到所有传送的剩余访问请求片段为止。

公开(公告)号：US20240143500A1

公开(公告)日：2024-05-02

申请号：US18207963

申请日：2023-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN JIN CHOI ,  SUNGHYUN NOH ,  INSOON JO ,  KUI-YON MUN ,  MYUNG-JIN JUNG

IPC: G06F12/02 ,  G06F12/0882

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F12/0882

Abstract: A memory system which includes a flash memory including a meta block and a data block, and a memory controller including a meta data managing module managing meta data to be stored in the meta block. The meta block includes a plurality of pages. The meta data managing module compares a number of free pages of the plurality of pages with a preset number of free pages, and selects a write target page of the meta data by using one of a consecution meta write operation or a dirty meta write operation, depending on a result of the comparison.

公开(公告)号：US20200183777A1

公开(公告)日：2020-06-11

申请号：US16533905

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BEOMKYU SHIN ,  KUI-YON MUN ,  SUNGKYU PARK

IPC: G06F11/10 ,  G11C11/409 ,  G11C29/52 ,  G11C29/34 ,  G06F13/16

Abstract: A memory system includes a memory device including memory cells, and a controller that performs a write operation, a read operation, and a check operation on the memory device. During the check operation, the controller controls the memory device to read check data from target memory cells of the memory cells by using a check level, compares the check data with original data stored in the target memory cells, and determines a reliability of the target memory cells or the check data based on a result of the comparison.

公开(公告)号：US20190004949A1

公开(公告)日：2019-01-03

申请号：US15871283

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  KUI-YON MUN ,  CHUL LEE

IPC: G06F12/084 ,  G06F3/06 ,  G06F13/16

Abstract: A system includes: a nonvolatile memory; a memory controller configured to control the nonvolatile memory, the memory controller including a first buffer memory for temporarily storing write data to be written to the nonvolatile memory; and a second buffer memory having a lower operational speed and a higher memory capacity than the first buffer memory. The memory controller is configured to transmit the write data from the first buffer memory to the second buffer memory and to the nonvolatile memory, and to release an operational state of the first buffer memory after transmitting the write data from the first buffer memory to the second buffer memory and to the nonvolatile memory. Writing additional write data to the first buffer memory is prohibited prior to the release of the operational state of the first buffer memory, and is permitted after the release of the operational state of the first buffer memory.