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公开(公告)号:US20180301178A1
公开(公告)日:2018-10-18
申请号:US15816810
申请日:2017-11-17
发明人: DAE-SHIK KIM , SUK-SOO PYO , GWAN-HYEOB KOH
CPC分类号: G11C11/1673 , G11C7/04 , G11C11/161 , G11C11/1697 , H01L27/228 , H01L43/08 , H01L43/10
摘要: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.
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公开(公告)号:US20190051351A1
公开(公告)日:2019-02-14
申请号:US15936696
申请日:2018-03-27
发明人: SUK-SOO PYO , Hyuntaek Jung , Taejoong Song
CPC分类号: G11C13/0028 , G11C5/147 , G11C7/14 , G11C7/227 , G11C8/08 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0026 , G11C13/003 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C2013/0054 , G11C2029/5006 , G11C2213/79 , G11C2213/82
摘要: A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells.
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公开(公告)号:US20190074045A1
公开(公告)日:2019-03-07
申请号:US15919876
申请日:2018-03-13
发明人: SUK-SOO PYO , Hyun-Taek Jung , Tae-Joong Song
IPC分类号: G11C11/16
CPC分类号: G11C11/1697 , G11C8/08 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
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