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    Memory modules and memory systems
    4.
    发明授权
    Memory modules and memory systems 有权
    内存模块和内存系统

    公开(公告)号：US09087614B2

    公开(公告)日：2015-07-21

    申请号：US14087167

    申请日：2013-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Pil Son ,  Uk-Song Kang ,  Chul-Woo Park ,  Young-Soo Sohn

    IPC: G11C7/12 ,  G11C29/44 ,  G06F11/10 ,  G11C29/00 ,  G11C5/04 ,  G11C29/04

    CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

    Abstract translation: 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。

    Repair control circuit and semiconductor memory device including the same
    5.
    发明授权
    Repair control circuit and semiconductor memory device including the same 有权
    修理控制电路和包括其的半导体存储器件

    公开(公告)号：US09007856B2

    公开(公告)日：2015-04-14

    申请号：US13804690

    申请日：2013-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Pil Son ,  Jae-Sung Kim ,  Uk-Song Kang ,  Young-Soo Sohn

    IPC: G11C7/00 ,  G11C29/04 ,  G11C29/44

    CPC classification number: G11C29/04 ,  G11C29/806 ,  G11C29/808 ,  G11C2029/4402

    Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

    Abstract translation: 控制半导体存储器件的修复操作的修复控制电路包括行匹配块和列匹配块。 行匹配块存储指示多个行组中的一个或多个故障行组的故障组信息。 通过对与多个字线对应的多个行地址进行分组来确定行组。 行匹配块基于输入行地址和故障组信息生成组匹配信号，使得组匹配信号指示包括输入行地址的故障行组。 列匹配块存储故障存储器单元的故障列地址，并且基于输入列地址，组匹配信号和故障列地址生成修复控制信号，使得修复控制信号指示是否执行修复操作或 不。

    Memory modules and memory systems
    7.
    发明授权
    Memory modules and memory systems 有权
    内存模块和内存系统

    公开(公告)号：US09558805B2

    公开(公告)日：2017-01-31

    申请号：US14083033

    申请日：2013-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Uk-Song Kang ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    IPC: G06F13/00 ,  G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40607 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4087

    Abstract: A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

    Abstract translation: 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

    Memory device, memory module, and memory system
    9.
    发明授权
    Memory device, memory module, and memory system 有权

    公开(公告)号：US09805802B2

    公开(公告)日：2017-10-31

    申请号：US15264774

    申请日：2016-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Pil Son ,  Uk-Song Kang

    IPC: G11C7/10 ,  G11C16/10 ,  G06F13/16

    CPC classification number: G11C16/102 ,  G06F13/16 ,  G06F13/1673

    Abstract: A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

    MEMORY DEVICE, MEMORY MODULE, AND MEMORY SYSTEM
    10.
    发明申请
    MEMORY DEVICE, MEMORY MODULE, AND MEMORY SYSTEM 有权
    存储器件，存储器模块和存储器系统

    公开(公告)号：US20170076768A1

    公开(公告)日：2017-03-16

    申请号：US15264774

    申请日：2016-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JONG-PIL SON ,  Uk-Song Kang

    IPC: G11C7/22 ,  G11C8/10 ,  G11C7/10

    CPC classification number: G11C16/102 ,  G06F13/16 ,  G06F13/1673

    Abstract: A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

    Abstract translation: 存储器件包括存储单元阵列，数据模式提供单元和写入电路。 存储单元阵列包括多个存储区域。 数据模式提供单元被配置为提供预定义的数据模式。 写入电路被配置为当从外部设备接收到第一写入命令和地址信号时，将从数据模式提供单元提供的预定义数据模式写入与地址信号对应的存储器区域。

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