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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200381546A1

    公开(公告)日：2020-12-03

    申请号：US16732864

    申请日：2020-01-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

    IPC分类号： H01L29/78 ,  H01L29/423

    摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220085202A1

    公开(公告)日：2022-03-17

    申请号：US17533499

    申请日：2021-11-23

    申请人： Samsung Electronics Co., Ltd.

    发明人： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

    IPC分类号： H01L29/78 ,  H01L29/423

    摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

    Semiconductor device and method of fabricating the same
    9.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11251313B2

    公开(公告)日：2022-02-15

    申请号：US16774653

    申请日：2020-01-28

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seung Mo Kang ,  Moon Seung Yang ,  Jongryeol Yoo ,  Sihyung Lee ,  Sunguk Jang ,  Eunhye Choi

    IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

    摘要： A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.