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公开(公告)号：US09245599B1
公开(公告)日：2016-01-26
申请号：US14887547
申请日：2015-10-20
Applicant: SANDISK 3D LLC
Inventor： Anurag Nigam , Gopinath Balakrishnan
CPC classification number: G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
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公开(公告)号：US09224466B1
公开(公告)日：2015-12-29
申请号：US14499717
申请日：2014-09-29
Applicant: SanDisk 3D LLC
Inventor： Yingchang Chen , Anurag Nigam
CPC classification number: G11C13/004 , G11C7/062 , G11C7/065 , G11C11/24 , G11C13/0023 , G11C13/0061 , G11C27/024 , G11C2213/71 , G11C2213/77
Abstract: Methods and apparatus are provided for reading a selected memory cell of a memory array using a sense amplifier that includes a first capacitor and a second capacitor. The selected memory cell is coupled to a bit line and a selected word line. A first noise voltage is generated on the first capacitor, and a selected memory cell voltage and a second noise voltage are generated on the second capacitor. The first noise voltage is an estimate of the second noise voltage. An output signal value is generated proportional to a difference between the selected memory cell voltage and a reference voltage, and a difference between the first noise voltage and second noise voltage. The output signal value is used to determine a data value for the selected memory cell.
Abstract translation: 提供了使用包括第一电容器和第二电容器的读出放大器读取存储器阵列的选定存储单元的方法和装置。 所选择的存储单元耦合到位线和所选择的字线。 在第一电容器上产生第一噪声电压，并且在第二电容器上产生选择的存储单元电压和第二噪声电压。 第一噪声电压是第二噪声电压的估计。 产生与选择的存储单元电压和参考电压之间的差成比例的输出信号值，以及第一噪声电压和第二噪声电压之间的差。 输出信号值用于确定所选存储单元的数据值。
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3.发明授权Leakage current compensation with reference bit line sensing in non-volatile memory 有权在非易失性存储器中使用参考位线检测的泄漏电流补偿公开(公告)号：US09390793B1
公开(公告)日：2016-07-12
申请号：US14663786
申请日：2015-03-20
Applicant: SanDisk 3D LLC
Inventor： Anurag Nigam , Yingchang Chen
CPC classification number: G11C13/004 , G11C7/06 , G11C7/062 , G11C7/08 , G11C13/0026 , G11C2013/0054
Abstract: A non-volatile memory includes a sense amplifier that uses a reference bit line. The sense amplifier includes a first capacitor coupled to a selected bit line and a second capacitor coupled to a reference bit line. The reference capacitor compensates for displacement currents in the selected bit line during sensing. Both plates of the capacitors are utilized to cancel leakage currents. The top plates of the capacitors are precharged then discharged during a sense phase. The selected bit line capacitor is discharged based on the selected cell current and the leakage current. The amount of discharge is transferred to the bottom plate of each capacitor, followed by discharging the bottom plates. The capacitor for the selected bit line is discharged based on the leakage current. In this manner, the correction phase facilitates a compensation based on the leakage current so that the selected cell current can be determined.
Abstract translation: 非易失性存储器包括使用参考位线的读出放大器。 感测放大器包括耦合到所选位线的第一电容器和耦合到参考位线的第二电容器。 参考电容器在感测期间补偿所选位线中的位移电流。 电容器的两个板都用于消除泄漏电流。 电容器的顶板预充电然后在感应阶段放电。 所选位线电容器根据选定的电池电流和漏电流放电。 放电量转移到每个电容器的底板，然后放电底板。 所选位线的电容器根据漏电流放电。 以这种方式，校正阶段有助于基于漏电流的补偿，使得可以确定所选择的单元电流。
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Patent Agency Ranking
公开(公告)号：US09196373B2
公开(公告)日：2015-11-24
申请号：US14191130
申请日：2014-02-26
Applicant: SANDISK 3D LLC
Inventor： Anurag Nigam , Gopinath Balakrishnan
CPC classification number: G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
Abstract translation: 描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。 读取操作可以包括预充电阶段，感测阶段和检测阶段。 在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测 相同的检测电路通过对检测电路的使用进行时间复用。 在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。
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公开(公告)号：US20150243362A1
公开(公告)日：2015-08-27
申请号：US14191130
申请日：2014-02-26
Applicant: SANDISK 3D LLC
Inventor： Anurag Nigam , Gopinath Balakrishnan
CPC classification number: G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
Abstract translation: 描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。 读取操作可以包括预充电阶段，感测阶段和检测阶段。 在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测 相同的检测电路通过对检测电路的使用进行时间复用。 在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。
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公开(公告)号：US09595323B1
公开(公告)日：2017-03-14
申请号：US15015672
申请日：2016-02-04
Applicant: SanDisk 3D LLC
Inventor： Yingchang Chen , Jeffrey Koonyee Lee , Chang Siau , Anurag Nigam , Thomas Yan
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/14 , G11C11/16 , G11C13/0028 , G11C13/0033 , G11C2013/0054
Abstract: A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at the selected word line voltage node based on the received current and the estimated resistance so that a voltage of the word line comb substantially equals a reference voltage.
Abstract translation: 提供一种用于操作非易失性存储系统的方法，该非易失性存储系统包括多个位线，包括多个字线的字线梳和多个存储元件，每个存储元件耦合在一个位线和一个位线之间 的字线。 该方法包括接收由字线梳传导的电流，估计字线梳与选定字线电压节点之间的导电路径的电阻，以及基于所接收的电流在所选字线电压节点处产生电压，以及 估计电阻使得字线梳的电压基本上等于参考电压。
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公开(公告)号：US20160276023A1
公开(公告)日：2016-09-22
申请号：US14663775
申请日：2015-03-20
Applicant: SanDisk 3D LLC
Inventor： Yingchang Chen , Anurag Nigam , Chang Siau
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1673 , G11C11/1675 , G11C13/0069 , G11C16/26 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2013/0088 , G11C2213/71
Abstract: A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.
Abstract translation: 描述了一种非易失性存储器，其包括读取放大器，其在读取操作期间将位线电压和读出放大器的输出保持在基本恒定的电压。 在预设相位期间，耦合到所选位线的读出放大器的输出端接地。 在预设阶段，至少有一个电容器被预充电。 在感测阶段期间，读出放大器输出与地面断开，而存储器阵列被偏置用于读取选定的存储单元。 所产生的电池电流由至少一个电容器集成。 集成电池电流基于所得到的电池电流将感测节点从预充电电平放电到精确的电压电平。
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公开(公告)号：US20160042771A1
公开(公告)日：2016-02-11
申请号：US14887547
申请日：2015-10-20
Applicant: SANDISK 3D LLC
Inventor： Anurag Nigam , Gopinath Balakrishnan
CPC classification number: G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
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