公开(公告)号：US20240121961A1

公开(公告)日：2024-04-11

申请号：US18348727

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiraku HASHIMOTO ,  Eisuke TAKII ,  Shin KOYAMA

IPC: H10B43/27 ,  H01L21/673 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/67303 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  C23C16/56

Abstract: A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

公开(公告)号：US20220157724A1

公开(公告)日：2022-05-19

申请号：US16952526

申请日：2020-11-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eisuke TAKII ,  Hiraku HASHIMOTO ,  Shin KOYAMA

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures. At least one silicon nitride liner prevents or reduces oxidation of the lower-level metal interconnect structures underneath the through-memory-level interconnection via structure.

公开(公告)号：US20170278859A1

公开(公告)日：2017-09-28

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Somesh PERI ,  Masanori TSUTSUMI ,  Keerti SHUKLA ,  Yusuke IKAWA ,  Kiyohiko SAKAKIBARA ,  Eisuke TAKII

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.