公开(公告)号：US20240237345A1

公开(公告)日：2024-07-11

申请号：US18355860

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyuki IWATA ,  Yusuke IKAWA ,  Kei SAMURA ,  Zhiwei CHEN

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, memory openings vertically extending through the second-tier alternating stack and the first-tier alternating stack, memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel including a respective portion of a semiconductor material, and hybrid support structures vertically extending at least through a respective subset of layers within the first-tier alternating stack. Each of the hybrid support structures includes a respective vertical stack of a dielectric support pillar and a composite support pillar having a respective dielectric outer surface and including a respective additional portion of the semiconductor material.

公开(公告)号：US20170278859A1

公开(公告)日：2017-09-28

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Somesh PERI ,  Masanori TSUTSUMI ,  Keerti SHUKLA ,  Yusuke IKAWA ,  Kiyohiko SAKAKIBARA ,  Eisuke TAKII

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US20170025421A1

公开(公告)日：2017-01-26

申请号：US15284067

申请日：2016-10-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Yusuke IKAWA

IPC: H01L27/115 ,  G11C16/04 ,  H01L29/10 ,  H01L29/06 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7391 ,  H01L29/868

Abstract: Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

Abstract translation: 通过测量通过垂直半导体通道的多数载流子电流，可以高速读取存储在三维存储器件中的多个电荷存储元件中的数据。 记忆膜设置在延伸穿过交替堆叠的绝缘层和导电层的存储器开口中。 具有第一导电类型的掺杂的一组掺杂半导体材料区域可以从衬底的顶表面下方连续地延伸通过存储膜到交替堆叠的最上层的水平。 阱接触通孔结构可以接触作为该掺杂半导体材料区域的元素的掺杂接触区域。 在掺杂的垂直半导体沟道和具有第二导电类型的掺杂的上掺杂半导体区之间的每个存储器开口内提供p-n结。