公开(公告)号：US20170236835A1

公开(公告)日：2017-08-17

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Jin LIU ,  Kazuya TOKUNAGA ,  Marika GUNJI-YONEOKA ,  Matthias BAENNINGER ,  Hiroyuki KINOSHITA ,  Murshed CHOWDHURY ,  Jiyin XU ,  Dai IWATA ,  Hiroyuki OGAWA ,  Kazutaka YOSHIZAWA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20230164995A1

公开(公告)日：2023-05-25

申请号：US17532015

申请日：2021-11-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kosaku YAMASHITA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. An insulating cap layer is formed thereupon. A memory opening is formed, which has a greater lateral dimension at a level of an upper insulating cap sublayer than at a level of a lower insulating cap sublayer. A memory film and a semiconductor channel material layer is formed in the memory opening. Ions of at least one dopant species is implanted into a top portion of the semiconductor channel material layer. An isotropic etch process etches an unimplanted portion of the semiconductor channel material layer at a higher etch rate than the implanted top portion of the semiconductor channel material layer to form a vertical semiconductor channel.