公开(公告)号：US20190391759A1

公开(公告)日：2019-12-26

申请号：US16289907

申请日：2019-03-01

Applicant: SK hynix Inc.

Inventor： Seok Joon KANG ,  Jin Su PARK ,  Ho Seok EM

IPC: G06F3/06 ,  G11C13/00

Abstract: A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

公开(公告)号：US20150043286A1

公开(公告)日：2015-02-12

申请号：US14082941

申请日：2013-11-18

Applicant: SK hynix Inc.

Inventor： Min Gi HONG ,  Jin Su PARK

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract translation: 一种半导体存储器件包括一个程序和读取单元，该程序和读取单元适用于对存储单元阵列中的程序数据进行编程，并用于读取存储在存储单元阵列中的读取数据;以及控制单元，适于产生用于控制程序和读取单元的控制信号 响应于从半导体存储器件的外部输入的命令，其中当输入读取命令时，控制单元控制程序和读取单元以在存储程序数据的第一位数据的状态下读取读取数据，同时 编程程序数据。

公开(公告)号：US20140177332A1

公开(公告)日：2014-06-26

申请号：US13845218

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Byoung Sung YOO ,  Jin Su PARK ,  Sang Don LEE

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/22 ,  G11C16/32

Abstract: A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents generation of an operating voltage by a pump circuit by preventing generation of a pump clock, and resets a microcontroller by preventing generation of micro clock. Accordingly, the semiconductor memory device may be prevented from malfunctioning through a series of operations when the external voltage is less than the reference voltage.

Abstract translation: 当外部电压小于参考电压时，当检测信号被输出时，通过控制就绪/繁忙的焊盘来保持半导体存储器件处于忙状态，通过防止泵的产生来防止泵电路产生工作电压 时钟，并通过防止微时钟的产生来重置微控制器。 因此，当外部电压小于参考电压时，可以通过一系列操作来防止半导体存储器件发生故障。

公开(公告)号：US20220189554A1

公开(公告)日：2022-06-16

申请号：US17357102

申请日：2021-06-24

Applicant: SK hynix Inc.

Inventor： Jin Su PARK

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26 ,  G11C5/06

Abstract: The disclosure relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including a plurality of memory strings, a pass circuit connected between local word lines of the memory block and global word lines and configured to connect the local word lines to the global word lines in response to a block selection signal, and a voltage providing circuit configured to generate an operation voltage during a program or read operation, apply the operation voltage to the global word lines, and discharge the global word lines when the program operation or the read operation is completed, and the pass circuit is configured to control the local word lines to be in a floating state after the program operation or the read operation is completed and before discharging the global word lines.

公开(公告)号：US20210050057A1

公开(公告)日：2021-02-18

申请号：US17084366

申请日：2020-10-29

Applicant: SK hynix Inc.

Inventor： Jin Su PARK

IPC: G11C13/00 ,  G11C5/14

Abstract: A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

公开(公告)号：US20200327939A1

公开(公告)日：2020-10-15

申请号：US16715343

申请日：2019-12-16

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Jin Su PARK

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.

公开(公告)号：US20190385644A1

公开(公告)日：2019-12-19

申请号：US16289981

申请日：2019-03-01

Applicant: SK hynix Inc.

Inventor： Seok Joon KANG ,  Jin Su PARK ,  Ho Seok EM

IPC: G11C5/06 ,  G11C5/14 ,  G11C13/00 ,  G05F3/02

Abstract: A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

公开(公告)号：US20190304540A1

公开(公告)日：2019-10-03

申请号：US16206901

申请日：2018-11-30

Applicant: SK hynix Inc.

Inventor： Jin Su PARK

IPC: G11C13/00 ,  G11C5/14

Abstract: A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

公开(公告)号：US20160163390A1

公开(公告)日：2016-06-09

申请号：US14691263

申请日：2015-04-20

Applicant: SK hynix Inc.

Inventor： Jin Su PARK

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block.

Abstract translation: 半导体器件包括包括多个存储器块的存储器阵列。 每个存储块包括管状晶体管，漏极选择晶体管和连接在管状晶体管和位线之间的第一存储单元，以及连接在管状晶体管和公共源极线之间的源极选择晶体管和第二存储单元。 该半导体器件还包括：操作电路，被配置为将工作电压施加到被选择执行编程和读取操作的存储器块;以及门控制电路，被配置为控制包括在未选择的存储器块中的管状晶体管的栅极。

公开(公告)号：US20190115079A1

公开(公告)日：2019-04-18

申请号：US16014306

申请日：2018-06-21

Applicant: SK hynix Inc.

Inventor： Jin Su PARK ,  Taek Seung KIM

IPC: G11C16/10 ,  G11C13/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C16/10 ,  G11C7/06 ,  G11C7/1069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2207/005 ,  G11C2213/76

Abstract: A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.