公开(公告)号：US09466360B2

公开(公告)日：2016-10-11

申请号：US14528636

申请日：2014-10-30

申请人： SK hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： G11C16/04 ,  G11C11/56

CPC分类号： G11C11/5635 ,  G11C11/5628 ,  G11C16/0483

摘要： A method of operating a semiconductor device includes performing a program operation on selected memory cells of a selected page, and selectively performing a soft erase operation on memory cells having threshold voltages greater than a reference voltage, among the selected memory cells, to reduce a width of a threshold voltage distribution of the selected memory cells.

摘要翻译： 一种操作半导体器件的方法包括对所选择的页面的选定的存储器单元执行编程操作，并且在所选择的存储单元中选择性地对具有大于参考电压的阈值电压的存储器单元执行软擦除操作，以减小宽度 所选择的存储单元的阈值电压分布。

公开(公告)号：US12125550B2

公开(公告)日：2024-10-22

申请号：US17502561

申请日：2021-10-15

申请人： SK hynix Inc.

发明人： Jun Hyuk Lee ,  Deung Kak Yoo ,  Dong Jae Jung ,  Min Kyu Lee

IPC分类号： G11C29/00 ,  G11C16/04 ,  G11C16/24 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C16/0483 ,  G11C16/24 ,  G11C2029/5004

摘要： The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

公开(公告)号：US09263596B2

公开(公告)日：2016-02-16

申请号：US14495558

申请日：2014-09-24

申请人： SK hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/1158 ,  H01L29/792 ,  H01L29/7926

摘要： A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

摘要翻译： 半导体器件包括沟道层，该沟道层包括具有在沟道层延伸的方向上彼此交替的突起和凹陷的侧壁，围绕沟道层的隧道绝缘层，围绕形成在凹陷中的隧道绝缘层的第一电荷存储图案 阻挡围绕形成在凹陷中的第一电荷图案的绝缘图案，其中阻挡绝缘图案包括连接到隧道绝缘层的连接部分和围绕形成在突起中的隧道绝缘层的第二电荷存储图案。

公开(公告)号：US09136275B2

公开(公告)日：2015-09-15

申请号：US14026788

申请日：2013-09-13

申请人： SK Hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L27/11556 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes at least one channel layer, insulating layers stacked on top of one another while surrounding the at least one channel layer, first grooves and second grooves alternately interposed between the insulating layers, wherein the first groves have a greater width than the second grooves having a second width, and conductive layers formed in the first grooves.

摘要翻译： 半导体器件包括至少一个沟道层，绝缘层彼此堆叠而围绕至少一个沟道层，交替插入在绝缘层之间的第一沟槽和第二沟槽，其中第一沟槽具有比第二沟道层更大的宽度 具有第二宽度的凹槽和形成在第一凹槽中的导电层。

公开(公告)号：US10424366B2

公开(公告)日：2019-09-24

申请号：US15613909

申请日：2017-06-05

申请人： SK hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： G11C11/26 ,  G11C11/4074 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C11/408 ,  H03K19/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

摘要： A semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.

公开(公告)号：US10424352B2

公开(公告)日：2019-09-24

申请号：US15934600

申请日：2018-03-23

申请人： SK hynix Inc.

发明人： Nam Hoon Kim ,  Soo Jin Wi ,  Deung Kak Yoo

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

摘要： There are provided a memory system and a method for operating the same. A memory system includes: a semiconductor memory device for outputting a ready/busy (R/B) signal by performing an internal operation in response to an operation command, and outputting status data by performing a status check operation in response to a status check command; and a controller for outputting the operation command and the status check command to the semiconductor memory device, and determining validity of the status data, based on the R/B signal.

公开(公告)号：US09001586B1

公开(公告)日：2015-04-07

申请号：US14219811

申请日：2014-03-19

申请人： SK Hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： G11C16/16 ,  G11C8/10

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/3445

摘要： A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.

摘要翻译： 根据本发明的实施例的半导体存储器件可以包括具有多个存储单元的存储单元阵列，具有耦合在全局字线和多个存储器单元之间的本地字线的正常通过晶体管的传输晶体管组 耦合的地址解码器和耦合到全局字线的地址解码器以及正常传输晶体管的栅极共同耦合的块字线，其中地址解码器逐渐增加通过从全局字线中减去全局字线的电压获得的电压 当擦除电压被提供给多个存储器单元的通道时，该块字线的电压。

公开(公告)号：US10437518B2

公开(公告)日：2019-10-08

申请号：US15936652

申请日：2018-03-27

申请人： SK hynix Inc.

发明人： Min Kyu Park ,  Soo Jin Wi ,  Deung Kak Yoo

IPC分类号： G11C5/14 ,  G06F3/06 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30

摘要： Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

公开(公告)号：US10180873B2

公开(公告)日：2019-01-15

申请号：US15642896

申请日：2017-07-06

申请人： SK hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： G06F11/07

摘要： Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. The memory cell array may include memory cells. The peripheral circuit may perform an operation for writing data to the memory cell array, reading data from the memory cell array, or erasing data written to the memory cell array. The control logic may control the peripheral circuit so that a data write operation, a data read operation or a data erase operation is performed. The status storage unit may store an operational status of the memory cell array as a first status value. The operating characteristic checking unit may receive an operating characteristic value, and generate a second status value via a comparison with an operation threshold value.

公开(公告)号：US09576977B2

公开(公告)日：2017-02-21

申请号：US14989346

申请日：2016-01-06

申请人： SK hynix Inc.

发明人： Deung Kak Yoo

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/1158 ,  H01L29/792 ,  H01L29/7926

摘要： A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

摘要翻译： 半导体器件包括沟道层，该沟道层包括具有在沟道层延伸的方向上彼此交替的突起和凹陷的侧壁，围绕沟道层的隧道绝缘层，围绕形成在凹陷中的隧道绝缘层的第一电荷存储图案 阻挡围绕形成在凹陷中的第一电荷图案的绝缘图案，其中阻挡绝缘图案包括连接到隧道绝缘层的连接部分和围绕形成在突起中的隧道绝缘层的第二电荷存储图案。