公开(公告)号：US11600599B2

公开(公告)日：2023-03-07

申请号：US17203354

申请日：2021-03-16

Applicant: SK hynix Inc.

Inventor： Tae Hoon Kim

IPC: H01L25/065

Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.

公开(公告)号：US11443805B2

公开(公告)日：2022-09-13

申请号：US17131456

申请日：2020-12-22

Applicant: SK hynix Inc.

Inventor： Sang Hyun Ban ,  Beom Seok Lee ,  Woo Tae Lee ,  Tae Hoon Kim ,  Hwan Jun Zang ,  Hye Jung Choi

IPC: G11C11/00 ,  G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells.

公开(公告)号：US09607699B2

公开(公告)日：2017-03-28

申请号：US14990272

申请日：2016-01-07

Applicant: SK hynix Inc.

Inventor： Tae Hoon Kim

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/1675 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2216/14

Abstract: An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a first program operation to the first one half page of a selected page with the first partial data; and performing a second program operation to the second one half page of the selected page with the second partial data. The first and second partial data may be programmed in the same first column region in the first and second one half pages, respectively.

公开(公告)号：US12295273B2

公开(公告)日：2025-05-06

申请号：US18590813

申请日：2024-02-28

Applicant: SK hynix Inc.

Inventor： Myoung Sub Kim ,  Tae Hoon Kim ,  Beom Seok Lee ,  Seung Yun Lee ,  Hwan Jun Zang ,  Byung Jick Cho ,  Ji Sun Han

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

公开(公告)号：US11996729B2

公开(公告)日：2024-05-28

申请号：US17461673

申请日：2021-08-30

Applicant: SK hynix Inc.

Inventor： Tae Hoon Kim ,  Jae Woong Jeong ,  Rak Hun Choi ,  Eun Kyu Choi ,  Tae Seung Han

IPC: H02J9/06 ,  H02J7/00 ,  H02J7/34

CPC classification number: H02J9/06 ,  H02J7/0068 ,  H02J7/345

Abstract: The present technology includes a power supply and a method of operating the same. The power supply includes a main power supply configured to receive external power and output a charge voltage and main power, and an auxiliary power supply including a capacitor array configured to charge auxiliary power using the charge voltage and output the auxiliary power. The auxiliary power supply is configured to periodically repeat a discharge operation and a sub charge operation on the capacitor array when the charging of the capacitor array is started.

公开(公告)号：US11950522B2

公开(公告)日：2024-04-02

申请号：US17847034

申请日：2022-06-22

Applicant: SK hynix Inc.

Inventor： Myoung Sub Kim ,  Tae Hoon Kim ,  Beom Seok Lee ,  Seung Yun Lee ,  Hwan Jun Zang ,  Byung Jick Cho ,  Ji Sun Han

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B61/00 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/011 ,  H10N70/231

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

公开(公告)号：US11482283B2

公开(公告)日：2022-10-25

申请号：US17214592

申请日：2021-03-26

Applicant: SK hynix Inc.

Inventor： Ki Won Lee ,  Seok Man Hong ,  Tae Hoon Kim ,  Hyung Dong Lee

IPC: G11C11/56 ,  G11C13/00

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

公开(公告)号：US20210110871A1

公开(公告)日：2021-04-15

申请号：US17131456

申请日：2020-12-22

Applicant: SK hynix Inc.

Inventor： Sang Hyun Ban ,  Beom Seok Lee ,  Woo Tae Lee ,  Tae Hoon Kim ,  Hwan Jun Zang ,  Hye Jung Choi

IPC: G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells.

公开(公告)号：US10978147B2

公开(公告)日：2021-04-13

申请号：US16669245

申请日：2019-10-30

Applicant: SK hynix Inc.

Inventor： Hyung Dong Lee ,  Tae Hoon Kim

IPC: G11C13/00 ,  G11C11/16

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.

公开(公告)号：US09728264B2

公开(公告)日：2017-08-08

申请号：US14789441

申请日：2015-07-01

Applicant: SK hynix Inc.

Inventor： Tae Hoon Kim

IPC: G06F12/00 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641

Abstract: A nonvolatile memory device includes a memory cell array including a data cell area, and a mode cell area that stores write mode information of the data cell area, a mode information storage block storing previous write mode information read out from the mode cell area in a previous read operation, and a control logic reading out the write mode information from the mode cell area comparing the read-out write mode information and the previous write mode information, and reading the data cell area in a read mode selected based on a comparison result.