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    Resistance variable memory device including stacked memory cells
    2.
    发明授权
    Resistance variable memory device including stacked memory cells 有权

    公开(公告)号：US11062769B2

    公开(公告)日：2021-07-13

    申请号：US17087080

    申请日：2020-11-02

    Applicant: SK hynix Inc.

    Inventor： Dong Keun Kim

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L43/10 ,  H01L27/24

    Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region. The second level of the word line at the selected row of the selected tile region and the first level of the bit line at the selected column of the selected tile region may be controlled by another decoding circuit of another tile region.

    Semiconductor apparatus
    4.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08824220B2

    公开(公告)日：2014-09-02

    申请号：US13736138

    申请日：2013-01-08

    Applicant: SK hynix Inc.

    Inventor： Hyun Joo Lee ,  Dong Keun Kim

    IPC: G11C7/00 ,  G11C13/00 ,  G11C7/06 ,  G11C7/08

    CPC classification number: G11C7/06 ,  G11C7/08 ,  G11C7/1045 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069

    Abstract: A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.

    Abstract translation: 半导体装置包括：响应于第一读取使能信号而在读取操作期间允许预定时间的读出放大器单元，其在响应于第二读取使能信号的写入操作之前被使能，并且当写入操作开始时被禁止， 以及开关单元，被配置为响应于第一选择信号在写入操作期间连接写入驱动器和存储器单元，响应于控制信号在读取操作期间将读出放大器单元和存储器单元连接预定时间， 并且当写入操作开始时断开读出放大器和存储器单元。

    Semiconductor apparatus
    6.
    发明授权
    Semiconductor apparatus 有权

    公开(公告)号：US11551780B2

    公开(公告)日：2023-01-10

    申请号：US15996005

    申请日：2018-06-01

    Applicant: SK hynix Inc.

    Inventor： Dong Keun Kim

    IPC: G11C16/06 ,  G11C29/00 ,  G11C29/44 ,  G11C29/24

    Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

    Memory device
    8.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09548111B2

    公开(公告)日：2017-01-17

    申请号：US14872908

    申请日：2015-10-01

    Applicant: KABUSHIKI KAISHA TOSHIBA ,  SK HYNIX, INC.

    Inventor： Masahiro Takahashi ,  Tsuneo Inaba ,  Dong Keun Kim ,  Ji Wang Lee

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.

    Abstract translation: 根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。 读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。 电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

    Semiconductor memory device and control method thereof
    9.
    发明授权
    Semiconductor memory device and control method thereof 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08780623B2

    公开(公告)日：2014-07-15

    申请号：US13864171

    申请日：2013-04-16

    Applicant: SK hynix Inc.

    Inventor： Ho Seok Em ,  Dong Keun Kim

    IPC: G11C11/00

    CPC classification number: G11C13/004 ,  G11C7/1048 ,  G11C7/12 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/02

    Abstract: A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.

    Abstract translation: 半导体存储器件基本上防止在读取操作中产生故障操作，并且增加了操作可靠性。 该半导体存储器件包括一个单元阵列，其被配置为包括响应于数据具有不同电阻值的存储元件，被配置为感测和放大数据的感测放大器，被配置为将感测放大器耦合到单元的全局位线 阵列和放电单元，其被配置为在执行读取操作之前对全局位线进行放电。

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