公开(公告)号：US20140117354A1

公开(公告)日：2014-05-01

申请号：US13796406

申请日：2013-03-12

Applicant: SK HYNIX INC.

Inventor： Chang-Il KIM ,  Sang-Eun LEE ,  Sung-Soo RYU ,  Seon-Kwang JEON

IPC: H01L23/50

CPC classification number: H01L25/18 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1076

Abstract: A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed.

Abstract translation: 一种半导体封装，包括：第一半导体封装，包括第一端子和第二端子，所述第一端子和第二端子设置在与形成有所述第一端子的表面不同的表面上;以及第二半导体封装，包括连接到所述第一端子的第三端子， 第一端子形成在其上形成有第三端子的表面。

公开(公告)号：US20190355707A1

公开(公告)日：2019-11-21

申请号：US16528938

申请日：2019-08-01

Applicant: SK hynix Inc.

Inventor： Sang-Eun LEE ,  Hyung-Dong LEE ,  Eun KO

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/78 ,  H01L25/065

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

公开(公告)号：US20180331087A1

公开(公告)日：2018-11-15

申请号：US15715449

申请日：2017-09-26

Applicant: SK hynix Inc.

Inventor： Sang-Eun LEE ,  Hyung-Dong LEE ,  Eun KO

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0612 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.