公开(公告)号：US20180240846A1

公开(公告)日：2018-08-23

申请号：US15648342

申请日：2017-07-12

Applicant: SK hynix Inc.

Inventor： Yong-Soo CHOI ,  Keun HEO ,  Hyung-Dong LEE

IPC: H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  G06N3/063

CPC classification number: H01L27/285 ,  B82Y10/00 ,  B82Y40/00 ,  G06N3/049 ,  G06N3/0635 ,  H01L51/0048 ,  H01L51/0583 ,  Y10S977/742

Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.

公开(公告)号：US20170194337A1

公开(公告)日：2017-07-06

申请号：US15394548

申请日：2016-12-29

Applicant: SK hynix Inc.

Inventor： Hyung-Dong LEE

IPC: H01L27/11521 ,  H01L27/11556 ,  G06N3/063 ,  H01L27/11519

CPC classification number: G06N3/063 ,  G11C11/54 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/40111 ,  H01L29/40117 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

Abstract: A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.

公开(公告)号：US20170186812A1

公开(公告)日：2017-06-29

申请号：US15182499

申请日：2016-06-14

Applicant: SK hynix Inc.

Inventor： Jong-Chul LEE ,  Beom-Yong KIM ,  Hyung-Dong LEE

IPC: H01L27/24 ,  G06F3/06 ,  H01L27/115 ,  H01L45/00 ,  H01L27/22

CPC classification number: H01L27/2427 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/224 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253

Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects

公开(公告)号：US20170148983A1

公开(公告)日：2017-05-25

申请号：US15136346

申请日：2016-04-22

Applicant: SK hynix Inc.

Inventor： Hyung-Dong LEE ,  Bong-Hoon LEE ,  Seong-Hyun KIM

IPC: H01L45/00 ,  G06F3/06

CPC classification number: H01L45/1233 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1253

Abstract: A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

公开(公告)号：US20160049582A1

公开(公告)日：2016-02-18

申请号：US14924342

申请日：2015-10-27

Applicant: SK hynix Inc.

Inventor： Wan-Gee KIM ,  Kee-Jeung LEE ,  Hyung-Dong LEE

IPC: H01L45/00 ,  G06F13/40 ,  G06F12/08 ,  G11C13/00 ,  G06F13/16

CPC classification number: H01L45/12 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2212/452 ,  G11C13/0007 ,  G11C13/0021 ,  G11C2213/54 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines.

公开(公告)号：US20140317332A1

公开(公告)日：2014-10-23

申请号：US14253971

申请日：2014-04-16

Applicant: SK hynix Inc.

Inventor： Hyung-Gyun YANG ,  Hyung-Dong LEE ,  Yong-Kee KWON ,  Young-Suk MOON ,  Hong-Sik KIM

IPC: G06F13/16 ,  G06F13/30

CPC classification number: G06F13/1673 ,  G06F13/1668 ,  G06F13/30

Abstract: A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Abstract translation: 半导体器件可以包括：存储单元，被配置为存储通过处理器核心的控制提供的程序代码; 以及控制单元，被配置为根据程序代码对半导体存储器件执行控制操作。

公开(公告)号：US20180349761A1

公开(公告)日：2018-12-06

申请号：US15810160

申请日：2017-11-13

Applicant: SK hynix Inc.

Inventor： Hyung-Dong LEE

IPC: G06N3/063

Abstract: A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.

公开(公告)号：US20170300810A1

公开(公告)日：2017-10-19

申请号：US15459622

申请日：2017-03-15

Applicant: SK Hynix Inc.

Inventor： Hyung-Dong LEE

IPC: G06N3/063 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: A neuromorphic device includes an input device; an output device; and a neural network including a first synapse network and a second synapse network between the input device and the output device. The first synapse network includes a first synapse system having higher learning efficiency than the second synapse network, and the second synapse network includes a second synapse system having more excellent data retention capability than the first synapse network.

公开(公告)号：US20170193363A1

公开(公告)日：2017-07-06

申请号：US15386920

申请日：2016-12-21

Applicant: SK hynix Inc.

Inventor： Hyung-Dong LEE

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a column spike to a second electrode of the memristor at a second time; inputting a row pulse to the drain electrode of the transistor at a third time that is delayed by a first delay time from the second time; inputting a column pulse to the second electrode of the memristor at a fourth time that is delayed by a second delay time from the second time; and inputting a gating pulse to a gate electrode of the transistor at a fifth time that is delayed by a third delay time from the fourth time.

公开(公告)号：US20170193359A1

公开(公告)日：2017-07-06

申请号：US15394524

申请日：2016-12-29

Applicant: SK hynix Inc.

Inventor： Sang-Su PARK ,  Hyung-Dong LEE

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/0635 ,  G06N3/049

Abstract: A neuromorphic device includes a substrate; a first electrode and a second electrode that are disposed over the substrate, extend in a first direction, and are spaced apart in a second direction; a stack structure between the first electrode and the second electrode, which includes reactive metal layers alternately stacked with one or more insulating layers; an oxygen-containing layer between the first electrode and the stack structure, which includes oxygen ions; and an oxygen diffusion-retarding layer between the stack structure and the oxygen-containing layer. The first direction is perpendicular to a top surface of the substrate, and the second direction is parallel to the top surface of the substrate. Each reactive metal layer may react with the oxygen ions to form a dielectric oxide layer. The oxygen diffusion-retarding layer interferes with a movement of the oxygen ions. A thickness of the oxygen diffusion-retarding layer varies along the first direction.