公开(公告)号：US20170076762A1

公开(公告)日：2017-03-16

申请号：US15053113

申请日：2016-02-25

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1069

Abstract: A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.

Abstract translation: 存储器件包括分别包括存储单元阵列和电耦合到存储单元阵列的本地输入/输出线的多个通道，并且是可独立操作的，电耦合到包括在存储单元阵列中的本地输入/输出线的共享全局输入/输出线 多个通道，并且具有通过一个或多个设置在多个通道中的路径切换电路而控制的连接关系，以及路径切换电路，其根据路径控制信号控制共享的全局输入/输出线的连接关系。

公开(公告)号：US20170062384A1

公开(公告)日：2017-03-02

申请号：US14951727

申请日：2015-11-25

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/73 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips. The semiconductor package may also include a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.

Abstract translation: 半导体封装可以包括以旋转对称结构设置的第一半导体芯片。 第一接合焊盘布置在第一半导体芯片的底表面上。 半导体封装还可以包括形成为围绕第一半导体芯片的至少侧表面的第一封装构件。 半导体封装还可以包括形成在第一封装构件中的通孔图案。 半导体封装还可以包括堆叠在第一半导体芯片的顶表面上的第二半导体芯片，以及包括通孔图案的第一封装构件，以便与第一半导体芯片形成台阶形状。 电连接到通孔图案的第二接合焊盘布置在第二半导体芯片的底表面上。 半导体封装还可以包括形成在第一半导体芯片的顶表面上的第二封装构件和第一封装构件，以围绕第二半导体芯片的至少侧表面。

公开(公告)号：US20170018527A1

公开(公告)日：2017-01-19

申请号：US14884916

申请日：2015-10-16

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/32145 ,  H01L2224/73267

Abstract: A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer. The semiconductor package may include coupling members interposed between the first bonding pads of the first semiconductor chip and the through vias of the reconfigurable package unit and between the respective through vias of the stacked reconfigurable package units.

Abstract translation: 半导体封装可以包括具有在第一有源表面上以第一间距布置的多个第一焊盘的第一半导体芯片。 半导体封装可以包括一个或多个可重新配置的封装单元，每个封装单元包括第二半导体芯片，该第二半导体芯片具有在第二有源表面上以第二间距布置的多个第二焊盘 半导体芯片连接器，与所述第二半导体芯片间隔开并且具有以所述第一间距排列的多个通孔; 围绕所述第二半导体芯片和所述半导体芯片连接器的侧表面的模制层; 以及形成在第二半导体芯片，半导体芯片连接器和模制层上的再分配线。 半导体封装可以包括插入在第一半导体芯片的第一接合焊盘和可重构封装单元的通孔之间以及堆叠的可重新配置封装单元的相应通孔之间的耦合构件。

公开(公告)号：US20190355707A1

公开(公告)日：2019-11-21

申请号：US16528938

申请日：2019-08-01

Applicant: SK hynix Inc.

Inventor： Sang-Eun LEE ,  Hyung-Dong LEE ,  Eun KO

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/78 ,  H01L25/065

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

公开(公告)号：US20180331087A1

公开(公告)日：2018-11-15

申请号：US15715449

申请日：2017-09-26

Applicant: SK hynix Inc.

Inventor： Sang-Eun LEE ,  Hyung-Dong LEE ,  Eun KO

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0612 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

公开(公告)号：US20170317056A1

公开(公告)日：2017-11-02

申请号：US15221920

申请日：2016-07-28

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/1436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/1703

Abstract: The present disclosure provides a semiconductor chip including a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip includes a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip includes a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.

公开(公告)号：US20170084575A1

公开(公告)日：2017-03-23

申请号：US14969241

申请日：2015-12-15

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.