公开(公告)号：US09478485B2

公开(公告)日：2016-10-25

申请号：US14261252

申请日：2014-04-24

Applicant: STATS ChipPAC, Ltd.

Inventor： XuSheng Bao ,  KwokKeung Szeto

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/14135 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/821 ,  H01L2224/8236 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2224/05664 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/13184 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯的周边区域中形成第一互连结构，例如包括形成在导电柱上的凸块的导电柱和第二互连结构。 第二半导体管芯设置在第一半导体管芯之间的第一互连结构和第二互连结构之间。 第二半导体管芯的高度小于第一互连结构的高度。 第二半导体管芯的占地面积小于第一半导体管芯的中心区域。 密封剂沉积在第一半导体管芯和第二半导体管芯上。 或者，第二半导体管芯设置在包括多个互连结构的半导体封装上。 执行单面fo-WLCSP的外部连接，而不使用导电通孔来提供高吞吐量和器件可靠性。

公开(公告)号：US20150001709A1

公开(公告)日：2015-01-01

申请号：US14261252

申请日：2014-04-24

Applicant: STATS ChipPAC, Ltd.

Inventor： XuSheng Bao ,  KwokKeung Szeto

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/14135 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/821 ,  H01L2224/8236 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2224/05664 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/13184 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯的周边区域中形成第一互连结构，例如包括形成在导电柱上的凸块的导电柱和第二互连结构。 第二半导体管芯设置在第一半导体管芯之间的第一互连结构和第二互连结构之间。 第二半导体管芯的高度小于第一互连结构的高度。 第二半导体管芯的占地面积小于第一半导体管芯的中心区域。 密封剂沉积在第一半导体管芯和第二半导体管芯上。 或者，第二半导体管芯设置在包括多个互连结构的半导体封装上。 执行单面fo-WLCSP的外部连接，而不使用导电通孔来提供高吞吐量和器件可靠性。